Traditionally,　the　precision　of　noise-shaping　(NS)　successive　approximation　register　(SAR)　analog-to-digital　converters　(ADCs)　is　limited　by　the　linearity　of　open-loop　residue　amplifier　and　it　is　challenging　to　achieve　high-order　(＞=　3)　noise-shaping.　To　mitigate　aforementioned　limitations,　we　innovatively　propose　a　fourth-order　NS　SAR　ADC,　which　adopts　the　2-2　hybrid　nested　(HN)　structure　that　nests　error　feedback　(EF)　and　cascaded　integrator　feed-forward　(CIFF).　With　the　aid　of　the　2-2　HN　structure,　a　process-voltage-temperature　(PVT)-robust　high-order　noise-shaping　has　been　successfully　implemented　in　NS　SAR　ADC.　Moreover,　to　achieve　high　precision:　(1)　The　closed-loop　cascode　floating　inverter　amplifier　(FIA)　is　employed　as　residue　amplifier,　breaking　the　tradeoff　between　linearity　of　dynamic　amplifier　and　high　precision　while　maintaining　high　power　efficiency,　and　realizing　a　truly　high-precision　NS　SAR　ADC　with　PVT　robustness.　(2)　Sampling　KT/C　noise　cancellation　(SNC)　technique　is　exploited　to　reduce　the　size　of　capacitive　digital-to-analog　converter　(CDAC)　while　meeting　the　same　precision　requirements.　The　proposed　ADC　was　prototyped　in　a　55　nm　CMOS　process,　achieving　a　high-precision　signal-to-noise-and-distortion　ratio　(SNDR)　of　92.6　dB,　capable　of　maintaining　SNDR　exceeding　90　dB　across　PVT　variations.　It　operates　within　a　312.5　kHz　bandwidth　(BW)　with　an　oversampling　ratio　(OSR)　of　8,　consuming　272　mu　W　power　under　1.2　V　supply　and　realizing　a　Schreier　figure　of　merit　(FoMs)　of　183　dB.