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学者姓名：胡炜
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Abstract ：
Significant advancements in artificial neural networks (ANNs) have driven the rapid progress of artificial intelligence and machine learning. While current feedforward neural networks primarily handle static data, recurrent neural networks (RNNs) are designed for dynamical systems. However, RNNs demand extensive training on specific tasks, limiting their scalability and affordability for edge computing. Physical reservoir computing (RC) offers an alternative approach by mapping inputs into high-dimensional states, allowing for pattern analysis within a fixed reservoir. Unlike RNNs, RC is well-suited for temporal and sequential data processing with rapid speed and low training costs. This makes RC suitable for hardware implementation across various research domains. Nonetheless, existing demonstrations of RC remain constrained to small-scale device arrays. As electronic synapse arrays aim to approach very large-scale and highly complex hardware as in the human brain, managing heat dissipation becomes a formidable challenge. In this work, we successfully developed the neuristors based on textured h-BN films, prepared using a CMOS-compatible technique, and constructed a physical RC system based on as-fabricated devices. Our approach leverages vertically aligned BN to provide aligned diffusion paths for the reproducible migration process of metal ions from the electrodes and offers a potential solution for thermal management in electronic devices. This achievement highlights the promising potential of our neuristors for future high-density and energy-efficient neuromorphic computing. © 2024 Elsevier B.V.
Keyword ：
Boron nitride Boron nitride Highly textured Highly textured High thermal conductivity High thermal conductivity Neuromorphic device Neuromorphic device Reservoir computing Reservoir computing
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| GB/T 7714 | Zhang, H. , Li, J. , Ju, X. et al. Highly textured CMOS-compatible hexagonal boron nitride-based neuristor for reservoir computing [J]. | Chemical Engineering Journal , 2024 , 498 . |
| MLA | Zhang, H. et al. "Highly textured CMOS-compatible hexagonal boron nitride-based neuristor for reservoir computing" . | Chemical Engineering Journal 498 (2024) . |
| APA | Zhang, H. , Li, J. , Ju, X. , Jiang, J. , Wu, J. , Chi, D. et al. Highly textured CMOS-compatible hexagonal boron nitride-based neuristor for reservoir computing . | Chemical Engineering Journal , 2024 , 498 . |
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针对物联网传感器难以同时满足高分辨率与低功耗的瓶颈问题，本文设计了一种伪三阶离散时间delta-sigma调制器.该架构将一阶无源噪声整形SAR(Successive Approximation Register)量化器嵌入传统二阶delta-sigma调制器以实现更强的噪声整形能力.本文设计允许系统在更低的过采样率（Over Sampling Ratio,OSR）下获取更高的峰值SQNR(Signal-to-Quantizing Noise Ratio)，有效缓解了系统精度和功耗之间的设计矛盾，并且减少了有源积分器的使用.针对传统有源加法器高功耗和无源加法器存在衰减不确定性的问题，本文提出了一种新型前馈求和量化电路，它具有对衰减不敏感的优势并且降低了第二级有源积分器的驱动压力，这进一步降低了系统的功耗.本文提出的delta-sigma调制器采用180 nm CMOS(Complementary Metal Oxide Semiconductor)工艺制造并测试.在电源电压1.4 V下，芯片测试功耗为47.2μW.在带宽为8 kHz的测试条件下，调制器的DR(Dynamic Range)、峰值SNDR(Signal-to-Noise and Distortion Ratio)和SFDR(Spurious-Free Dynamic Range)分别为97.2 dB,96.6 dB和114.4 dB.因此，Schreier和Walden的SNDR FoM(Figure of Merit)优值达到了178.9 dB和0.053 pJ/step.本文提出的伪三阶delta-sigma调制器在功耗和分辨率之间实现了较好的权衡，为物联网领域的低功耗高分辨率调制器设计提供了较好的解决方案.
Keyword ：
delta-sigma调制器 delta-sigma调制器 低功耗 低功耗 物联网 物联网 高分辨率 高分辨率
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| GB/T 7714 | 魏聪 , 黄黎杰 , 胡炜 et al. 一种应用于物联网传感器的伪三阶Delta-Sigma调制器 [J]. | 电子学报 , 2024 , 52 (06) : 2123-2130 . |
| MLA | 魏聪 et al. "一种应用于物联网传感器的伪三阶Delta-Sigma调制器" . | 电子学报 52 . 06 (2024) : 2123-2130 . |
| APA | 魏聪 , 黄黎杰 , 胡炜 , 魏榕山 . 一种应用于物联网传感器的伪三阶Delta-Sigma调制器 . | 电子学报 , 2024 , 52 (06) , 2123-2130 . |
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The next-generation computing system is required to perform 10(18) floating point operations per second to address the exponential growth of data from sensory terminals, driven by advancements in artificial intelligence and the Internet of Things. Even if a supercomputer possesses the capability to execute these operations, managing heat dissipation becomes a significant challenge when the electronic synapse array reaches a comparable scale with the human neuron network. One potential solution to address thermal hotspots in electronic devices is the use of vertically-aligned hexagonal boron nitride (h-BN) known for its high thermal conductivity. In this study, we have developed textured h-BN films using the high power impulse magnetron sputtering technique. The thermal conductivity of the oriented h-BN film is approximately 354% higher than that of the randomly oriented counterpart. By fabricating electronic synapses based on the textured h-BN thin film, we demonstrate various bio-synaptic plasticity in this device. Our results indicate that orientation engineering can effectively enable h-BN to function as a suitable self-heat dissipation layer, thereby paving the way for future wearable memory devices, solar cells, and neuromorphic devices.
Keyword ：
boron nitride boron nitride high thermal conductivity high thermal conductivity low-power memory low-power memory neuromorphic computing neuromorphic computing vertically-aligned vertically-aligned
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| GB/T 7714 | Zhang, Haizhong , Ju, Xin , Jiang, Haitao et al. Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor [J]. | SCIENCE CHINA-MATERIALS , 2024 , 67 (6) : 1907-1914 . |
| MLA | Zhang, Haizhong et al. "Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor" . | SCIENCE CHINA-MATERIALS 67 . 6 (2024) : 1907-1914 . |
| APA | Zhang, Haizhong , Ju, Xin , Jiang, Haitao , Yang, Dan , Wei, Rongshan , Hu, Wei et al. Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor . | SCIENCE CHINA-MATERIALS , 2024 , 67 (6) , 1907-1914 . |
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This paper proposes a pseudo third-order discrete-time delta-sigma modulator to address the bottleneck of high resolution and low power consumption in Internet of Things (IoT) sensors. This architecture embeds a first-order passive noise-shaping SAR (Successive Approximation Register) quantizer into a conventional second-order delta-sigma modulator to achieve stronger noise-shaping capabilities. This allows the system to achieve higher peak SQNR (Signal-to-Quantizing Noise Ratio) at lower OSR (Over Sampling Ratio), effectively mitigating the design trade-off between system accuracy and power consumption, while reducing the use of active integrators. In response to the high power consumption of traditional active adders and the attenuation uncertainty of passive adders, this paper proposes a novel feedforward sum quantization circuit. It has the advantage of being insensitive to attenuation and reduces the driving pressure of the second stage active integrator, which further reduces the power consumption of the system. The proposed delta-sigma modulator is manufactured and tested using a 180 nm CMOS (Complementary Metal Oxide Semiconductor) process. At a power supply voltage of 1.4 V, the tested power consumption of the chip is 47.2 μW. With a bandwidth of 8 kHz, the DR (Dynamic Range), peak SNDR (Signal-to-Noise and Distortion Ratio), and SFDR (Spurious-Free Dynamic Range) of the modulator are 97.2 dB, 96.6 dB, and 114.4 dB, respectively. Therefore, figure-of-merit (FoM) Schreier and Walden for SNDR are 178.9 dB and 0.053 pJ/step. The pseudo third-order delta-sigma modulator proposed in this article achieves a good balance between power consumption and resolution, providing a good solution for low-power and high-resolution modulator design in the field of the IoTs. © 2024 Chinese Institute of Electronics. All rights reserved.
Keyword ：
delta-sigma modulator delta-sigma modulator high resolution high resolution internet of things internet of things low power low power
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| GB/T 7714 | Wei, C. , Huang, L.-J. , Hu, W. et al. Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors; [一种应用于物联网传感器的伪三阶Delta-Sigma 调制器] [J]. | Acta Electronica Sinica , 2024 , 52 (6) : 2123-2130 . |
| MLA | Wei, C. et al. "Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors; [一种应用于物联网传感器的伪三阶Delta-Sigma 调制器]" . | Acta Electronica Sinica 52 . 6 (2024) : 2123-2130 . |
| APA | Wei, C. , Huang, L.-J. , Hu, W. , Wei, R.-S. . Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors; [一种应用于物联网传感器的伪三阶Delta-Sigma 调制器] . | Acta Electronica Sinica , 2024 , 52 (6) , 2123-2130 . |
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电流反馈仪表放大器芯片因其高精度、高共模抑制比等优势,广泛应用于微弱信号检测.传统CFIA利用斩波技术降低 1/f 噪声和失调电压以提升放大器精度,但额外引入斩波波纹会显著限制其精度提升.为此,本文提出一种基于自适应时钟和波纹减小环路的新型电流反馈仪表放大器ARCFIA,该放大器针对传统斩波放大器波纹,采用波纹减少环路RRL对其抑制,并借助自适应时钟ACLK,将斩波开关的输入参考噪声谱密度降低.实验结果表明,ARCFIA实现了低于 1.4 μV的低失调电压和 17.2 nV/Hz的输入参考噪声,同时波纹被减少到ARCFIA噪声基底以下,通过减小失调、噪声和波纹,实现了精度的进一步提升.此外,ARCFIA还具有一定潜力应用于复杂环境下的高精度测量系统.
Keyword ：
低噪声 低噪声 低失调 低失调 波纹减少 波纹减少 电流反馈仪表放大器 电流反馈仪表放大器 自适应时钟 自适应时钟 高精度 高精度
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| GB/T 7714 | 胡炜 , 吴展鹏 , 程捷文 et al. 一种基于自适应时钟和波纹减少环路的高精度电流反馈仪表放大器 [J]. | 仪器仪表学报 , 2024 , 45 (8) : 259-267 . |
| MLA | 胡炜 et al. "一种基于自适应时钟和波纹减少环路的高精度电流反馈仪表放大器" . | 仪器仪表学报 45 . 8 (2024) : 259-267 . |
| APA | 胡炜 , 吴展鹏 , 程捷文 , 魏榕山 . 一种基于自适应时钟和波纹减少环路的高精度电流反馈仪表放大器 . | 仪器仪表学报 , 2024 , 45 (8) , 259-267 . |
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Conventional sense amplifiers limit the performance of current RRAM computing-in-memory (CIM) macro circuits, resulting in high latency and energy consumption. This paper introduces a multi-bit quantization technology low-latency voltage sense amplifier (MQL-VSA). Firstly, the multi-bit quantization technology enhances circuit quantization efficiency, reducing the number of operational states in conventional VSA. Secondly, by simplifying the sequential logic circuits in conventional VSA, the complexity of sequential control signals is reduced, further diminishing readout latency. Experimental results demonstrate that the MQL-VSA achieves a 1.40-times decrease in readout latency and a 1.28-times reduction in power consumption compared to conventional VSA. Additionally, an 8-bit input, 8-bit weight, 14-bit output macro circuit utilizing MQL-VSA exhibited a 1.11times latency reduction and 1.04-times energy savings.
Keyword ：
computing-in-memory computing-in-memory low latency low latency RRAM RRAM voltage sense amplifier voltage sense amplifier
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| GB/T 7714 | Hu, Wei , Zhang, Hangze , Wei, Rongshan et al. A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits [J]. | ELECTRONICS , 2024 , 13 (2) . |
| MLA | Hu, Wei et al. "A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits" . | ELECTRONICS 13 . 2 (2024) . |
| APA | Hu, Wei , Zhang, Hangze , Wei, Rongshan , Chen, Qunchao . A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits . | ELECTRONICS , 2024 , 13 (2) . |
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存内计算（Computing In Memory,CIM）在人工智能神经网络的卷积运算方面具有巨大的应用潜力。基于忆阻器阵列的多位存内计算由于具备写入速度快、与互补金属氧化物半导体（Complementary Metal Oxide Semiconductor, CMOS）工艺兼容等特点，有望成为解决“内存墙”的有效手段。然而，当前多位存内计算电路架构面临输出延时高和能耗大的问题，主要原因为传统感知放大器的性能制约，为此本文提出了一种低延时低能耗多位电流型感知放大器（Low-delay Low-power Multi-bit Current-mode Sense Amplifier,LLM-CSA），通过减少传统CSA电路工作状态数量、简化工作时序来优化功能；采用新型低位检测模块的电路设计思路，来多层次系统性地降低输出延时并优化能耗。使用中芯国际40 nm低漏电逻辑工艺（SMIC40 nm LL），利用Cadence电路设计平台，仿真验证所提LLM-CSA的功能和延时-能耗性能。通过对比分析发现：LLM-CSA比传统CSA输出延时降低1.42倍，能量消耗降低1.56倍。进一步地，以一种4 bit输入、4 bit权重、11 bit输出的忆阻器阵列多位存内计算架构为应用，对比验证所提LLM-CSA的性能：与基于传统CSA的存内计算系统相比，新架构延时降低1.18倍，能耗降低1.03倍。LLM-CSA的提出对促进感知放大器设计思路和忆阻器阵列存内计算架构的发展，具有一定的理论和现实意义。
Keyword ：
低延时低能耗 低延时低能耗 存内计算 存内计算 忆阻器阵列 忆阻器阵列 电流型感知放大器 电流型感知放大器
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| GB/T 7714 | 唐成峰 , 胡炜 . 应用于忆阻器阵列存内计算的低延时低能耗新型感知放大器 [J]. | 微电子学与计算机 , 2024 , (02) : 58-66 . |
| MLA | 唐成峰 et al. "应用于忆阻器阵列存内计算的低延时低能耗新型感知放大器" . | 微电子学与计算机 02 (2024) : 58-66 . |
| APA | 唐成峰 , 胡炜 . 应用于忆阻器阵列存内计算的低延时低能耗新型感知放大器 . | 微电子学与计算机 , 2024 , (02) , 58-66 . |
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本工作通过微磁学模拟数值计算证实了以超低电流密度驱动拓扑绝缘体/楔形铁磁异质结构实现确定性无场切换是可行的。此外，我们研究了楔形铁磁层尺寸、界面Dzyaloshinskii-Moriya相互作用、类场转矩和倾斜垂直磁各向异性的偏离极角等因素对自旋轨道矩无场切换的影响。综合优化各个因素后，拓扑绝缘体(BiSb)/楔形铁磁异质结构的临界切换电流密度最低可降至9.0×10~6 A/cm~2,比传统重金属/铁磁结构的临界切换电流密度降低了1～2个数量级。这项研究对于推动低功耗自旋轨道矩磁性随机存储器的产业化应用具有重要的意义。
Keyword ：
垂直磁各向异性 垂直磁各向异性 微磁学模拟 微磁学模拟 拓扑绝缘体 拓扑绝缘体 无场切换 无场切换 自旋轨道矩 自旋轨道矩
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| GB/T 7714 | 邱鹏 , 朱敏敏 , 胡炜 et al. BiSb/楔形铁磁结构中的自旋轨道矩无场切换 [J]. | 功能材料与器件学报 , 2024 , 30 (04) : 197-205 . |
| MLA | 邱鹏 et al. "BiSb/楔形铁磁结构中的自旋轨道矩无场切换" . | 功能材料与器件学报 30 . 04 (2024) : 197-205 . |
| APA | 邱鹏 , 朱敏敏 , 胡炜 , 张海忠 . BiSb/楔形铁磁结构中的自旋轨道矩无场切换 . | 功能材料与器件学报 , 2024 , 30 (04) , 197-205 . |
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This paper presents a BJT-based smart CMOS temperature sensor. The analog front-end circuit contains a bias circuit and a bipolar core; the data conversion interface features an incremental delta-sigma analog-to-digital converter. The circuit utilizes the chopping, correlated double sampling, and dynamic element matching techniques to mitigate the effects of process bias and nonideal device characteristics on measurement accuracy. Furthermore, based on the principle of charge conservation, the dynamic range utilization of the ADC increases. We propose a neural network that uses a multilayer convolutional perceptron to calibrate the sensor output results. Using the algorithm, the sensor achieves an inaccuracy of +/- 0.11 degrees C (3 sigma), exceeding the accuracy of +/- 0.23 degrees C (3 sigma) achieved without calibration. We implement the sensor in a 0.18 mu m CMOS process, occupying an area of 0.42 mm(2). It achieves a resolution of 0.01 degrees C and has a conversion time of 24 ms.
Keyword ：
calibration calibration delta-sigma modulation delta-sigma modulation high precision high precision neural network neural network temperature sensor temperature sensor
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| GB/T 7714 | Wei, Rongshan , Lin, Huishan , Chen, Qunchao et al. A CMOS Temperature Sensor with a Smart Calibrated Inaccuracy of +/- 0.11 (3 sigma) [J]. | SENSORS , 2023 , 23 (11) . |
| MLA | Wei, Rongshan et al. "A CMOS Temperature Sensor with a Smart Calibrated Inaccuracy of +/- 0.11 (3 sigma)" . | SENSORS 23 . 11 (2023) . |
| APA | Wei, Rongshan , Lin, Huishan , Chen, Qunchao , Huang, Gongxing , Hu, Wei . A CMOS Temperature Sensor with a Smart Calibrated Inaccuracy of +/- 0.11 (3 sigma) . | SENSORS , 2023 , 23 (11) . |
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This paper presents a single bit continuous time delta-sigma modulator (CTDSM) with finite impulse response (FIR) feedback DAC designed for audio applications. By using FIR feedback in the input stage, the linearity requirements of the first integrator are relaxed, and the clock jitter sensitivity is reduced, as seen in a multi-bit quantizers. The choppers, working in conjunction with the FIR DAC, effectively suppresses in-band aliasing noise generated by the chopper in the first integrator. A fast comparator serves as a single-bit quantizer, and the 9.2% TS loop delay eliminates the need for excess loop delay compensation in the modulator. Energy efficient in-tegrators are implemented using the current-starved OTA. The CTDSM prototype was fabricated using a 180-nm CMOS process, achieving a 90.5 dB SNDR and 96 dB DR with a 24 kHz signal bandwidth. The power con-sumption is 210 & mu; W, corresponding to a Schreier figure-of-merit value of 171.1 dB.
Keyword ：
Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) Continuous-time Continuous-time Delta -sigma modulator Delta -sigma modulator Finite impulse response Finite impulse response Noise-shaping Noise-shaping Oversampling Oversampling
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| GB/T 7714 | Wei, Rongshan , Huang, Gongxing , Hu, Wei et al. A 24-kHz BW 90.5-dB SNDR 96-dB DR continuous-time delta-sigma modulator using FIR DAC feedback [J]. | MICROELECTRONICS JOURNAL , 2023 , 138 . |
| MLA | Wei, Rongshan et al. "A 24-kHz BW 90.5-dB SNDR 96-dB DR continuous-time delta-sigma modulator using FIR DAC feedback" . | MICROELECTRONICS JOURNAL 138 (2023) . |
| APA | Wei, Rongshan , Huang, Gongxing , Hu, Wei , Wei, Cong , Lin, Huishan . A 24-kHz BW 90.5-dB SNDR 96-dB DR continuous-time delta-sigma modulator using FIR DAC feedback . | MICROELECTRONICS JOURNAL , 2023 , 138 . |
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