This　paper　presents　a　cascode　OTA　assisted　by　a　floating　inverter　amplifier,　which　offers　high　gain　with　reduced　power　consumption　and　excellent　linearity.　In　comparison　to　conventional　cascode　OTA,　it　achieves　approximately　30　%　power　savings　while　maintaining　the　same　level　of　linearity.　To　address　the　limited　output　swing　of　the　cascode　OTA,　the　finite　impulse　response　(FIR)　DAC　technique,　which　is　widely　used　in　CTDSM,　is　introduced　in　the　DTDSM.　The　FIR　DAC　output　resembles　that　of　a　multibit　DAC　without　requiring　a　mismatch　shaping　circuit.　By　incorporating　FIR　DAC,　we　effectively　scale　up　integrator　coefficients　and　decrease　power　consumption　of　the　first-stage　integrator.　A　prototype　was　fabricated　in　a　0.18-mu　m　CMOS　process　with　an　active　area　of　0.2　mm2,　achieving　peak　SNDR/DR　values　of　94.5　and　96.5　dB　while　consuming　only　190　mu　W　of　power.