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学者姓名：魏榕山
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The Ordered Escape Routing (OER) problem, which is an NP-hard problem, is critical to PCB design. Primary methods based on integer linear programming (ILP) work well on small-scale PCBs with fewer pins. However, when dealing with large-scale instances, traditional ILP strategies frequently cause time violations as the number of variables increases due to time-consuming preprocessing. In addition, heuristic algorithms have a time advantage when dealing with specific problems. In this paper, We propose an efficient two-stage escape routing method that employs LP for global routing and uses a heuristic algorithm to deal with the path intersection problem to minimize wiring length and runtime for large-scale PCBs. We first model the OER problem as a min-cost multi-commodity flow problem and use ILP to solve it. Then, we relax the non-crossing constraints and transform the ILP model into an LP model to reduce the runtime. we also construct a crossing graph according to the intersection of routing paths and propose a heuristic algorithm to locate congestion quickly. Finally, we reduce the local area capacity and allow global automatic congestion optimization. Compared with the state-of-the-art work, experimental results show that our method can reduce the routing time by 60% and handle larger-scale PCB escape routing problems.
Keyword ：
Heuristic algorithm Heuristic algorithm Linear programming Linear programming Min-cost multi-commodity flow Min-cost multi-commodity flow Ordered escape routing Ordered escape routing
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| GB/T 7714 | Lin, Disi , Chen, Chuandong , Wei, Rongshan et al. Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB [J]. | INTEGRATION-THE VLSI JOURNAL , 2025 , 100 . |
| MLA | Lin, Disi et al. "Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB" . | INTEGRATION-THE VLSI JOURNAL 100 (2025) . |
| APA | Lin, Disi , Chen, Chuandong , Wei, Rongshan , Liu, Qinghai , He, Huan , Zhu, Ziran et al. Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB . | INTEGRATION-THE VLSI JOURNAL , 2025 , 100 . |
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For high-precision sensor applications, high dynamic range discrete-time delta-sigma modulators (DSMs) are key components. For the design of high dynamic range DSMs, the system architecture is crucial. The system requires strong in-band noise suppression for small input amplitudes and a large maximum stable amplitude (MSA) for large input amplitudes. This article presents the system design and optimization method of discrete- time delta-sigma modulator. It provides a detailed discussion on the behavior-level modeling and characteristics of low-bit and multi-bit quantizers. Additionally, design considerations of quantizers in DSM systems are analyzed. An approach for optimizing DSM systems by leveraging the properties of quantizers is proposed, along with a simple optimization case study. Potential future application scenarios are also presented. The purpose of this article is to offer design guidelines for developing well-performing DSMs systems.
Keyword ：
Delta-sigma modulator (DSM) Delta-sigma modulator (DSM) Discrete-time Discrete-time Dynamic range Dynamic range Quantizer Quantizer
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| GB/T 7714 | Peng, Ziqiang , Wei, Cong , Huang, Lijie et al. Design and optimization of discrete-time delta-sigma modulators [J]. | MICROELECTRONICS JOURNAL , 2025 , 156 . |
| MLA | Peng, Ziqiang et al. "Design and optimization of discrete-time delta-sigma modulators" . | MICROELECTRONICS JOURNAL 156 (2025) . |
| APA | Peng, Ziqiang , Wei, Cong , Huang, Lijie , Lai, Jinze , Lu, Xiaoqiang , Wei, Rongshan . Design and optimization of discrete-time delta-sigma modulators . | MICROELECTRONICS JOURNAL , 2025 , 156 . |
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This paper proposes a fully dynamic zoom ADC based on residue feedforward and correlated level shifting (CLS)-assisted floating inverter amplifier (FIA) technique with 200 × bandwidth/power scalability, by only changing the clock frequency. A CLS-assisted FIA which achieves 65 dB DC gain is employed to reduce errors from finite FIA gain. An energy-efficient residue feedforward path extracted from the input of the SAR ADC's comparator minimizes the leakage of the SAR ADC's quantization noise into the band. A novel two-step summation approach is proposed to minimize capacitor areas compared to a traditional passive switched-capacitor adder. The post-simulated results show the prototype ADC with near-constant energy efficiency, which scales power from 5 μW to 822 μW, achieves high resolution (>100 dB) during the scalable bandwidth. At 20 kHz BW, it achieves 106.2 dB DR, 102.0 dB SNDR, leading to FoMDR of 180.0 dB and FoMSNDR of 175.8 dB. © 2024
Keyword ：
Capacitor bank Capacitor bank Capacitors Capacitors Comparators (optical) Comparators (optical)
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| GB/T 7714 | Wei, Rongshan , Zheng, Zhijian , Lin, Yuxuan et al. Fully dynamic zoom ADC with energy-efficient residue feedforward and two-step summation [J]. | Microelectronics Journal , 2024 , 154 . |
| MLA | Wei, Rongshan et al. "Fully dynamic zoom ADC with energy-efficient residue feedforward and two-step summation" . | Microelectronics Journal 154 (2024) . |
| APA | Wei, Rongshan , Zheng, Zhijian , Lin, Yuxuan , Xu, Nannan , Zhao, Gumeng , Chen, Qunchao . Fully dynamic zoom ADC with energy-efficient residue feedforward and two-step summation . | Microelectronics Journal , 2024 , 154 . |
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Significant advancements in artificial neural networks (ANNs) have driven the rapid progress of artificial intelligence and machine learning. While current feedforward neural networks primarily handle static data, recurrent neural networks (RNNs) are designed for dynamical systems. However, RNNs demand extensive training on specific tasks, limiting their scalability and affordability for edge computing. Physical reservoir computing (RC) offers an alternative approach by mapping inputs into high-dimensional states, allowing for pattern analysis within a fixed reservoir. Unlike RNNs, RC is well-suited for temporal and sequential data processing with rapid speed and low training costs. This makes RC suitable for hardware implementation across various research domains. Nonetheless, existing demonstrations of RC remain constrained to small-scale device arrays. As electronic synapse arrays aim to approach very large-scale and highly complex hardware as in the human brain, managing heat dissipation becomes a formidable challenge. In this work, we successfully developed the neuristors based on textured h-BN films, prepared using a CMOS-compatible technique, and constructed a physical RC system based on as-fabricated devices. Our approach leverages vertically aligned BN to provide aligned diffusion paths for the reproducible migration process of metal ions from the electrodes and offers a potential solution for thermal management in electronic devices. This achievement highlights the promising potential of our neuristors for future high-density and energy-efficient neuromorphic computing. © 2024 Elsevier B.V.
Keyword ：
Boron nitride Boron nitride Highly textured Highly textured High thermal conductivity High thermal conductivity Neuromorphic device Neuromorphic device Reservoir computing Reservoir computing
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| GB/T 7714 | Zhang, H. , Li, J. , Ju, X. et al. Highly textured CMOS-compatible hexagonal boron nitride-based neuristor for reservoir computing [J]. | Chemical Engineering Journal , 2024 , 498 . |
| MLA | Zhang, H. et al. "Highly textured CMOS-compatible hexagonal boron nitride-based neuristor for reservoir computing" . | Chemical Engineering Journal 498 (2024) . |
| APA | Zhang, H. , Li, J. , Ju, X. , Jiang, J. , Wu, J. , Chi, D. et al. Highly textured CMOS-compatible hexagonal boron nitride-based neuristor for reservoir computing . | Chemical Engineering Journal , 2024 , 498 . |
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Abstract ：
This paper proposes a fully dynamic zoom ADC based on residue feedforward and correlated level shifting (CLS)-assisted floating inverter amplifier (FIA) technique with 200 x bandwidth/power scalability, by only changing the clock frequency. A CLS-assisted FIA which achieves 65 dB DC gain is employed to reduce errors from finite FIA gain. An energy-efficient residue feedforward path extracted from the input of the SAR ADC's comparator minimizes the leakage of the SAR ADC's quantization noise into the band. A novel two-step summation approach is proposed to minimize capacitor areas compared to a traditional passive switched-capacitor adder. The post-simulated results show the prototype ADC with near-constant energy efficiency, which scales power from 5 mu W to 822 mu W, achieves high resolution (>100 dB) during the scalable bandwidth. At 20 kHz BW, it achieves 106.2 dB DR, 102.0 dB SNDR, leading to FoM(DR) of 180.0 dB and FoM(SNDR) of 175.8 dB.
Keyword ：
Correlated level shifting Correlated level shifting Dynamic Dynamic Floating inverter amplifier Floating inverter amplifier Residue feedforward Residue feedforward Two-step summation Two-step summation Zoom ADC Zoom ADC
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| GB/T 7714 | Wei, Rongshan , Zheng, Zhijian , Lin, Yuxuan et al. Fully dynamic zoom ADC with energy-efficient residue feedforward and two-step summation [J]. | MICROELECTRONICS JOURNAL , 2024 , 154 . |
| MLA | Wei, Rongshan et al. "Fully dynamic zoom ADC with energy-efficient residue feedforward and two-step summation" . | MICROELECTRONICS JOURNAL 154 (2024) . |
| APA | Wei, Rongshan , Zheng, Zhijian , Lin, Yuxuan , Xu, Nannan , Zhao, Gumeng , Chen, Qunchao . Fully dynamic zoom ADC with energy-efficient residue feedforward and two-step summation . | MICROELECTRONICS JOURNAL , 2024 , 154 . |
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This paper presents a cascode OTA assisted by a floating inverter amplifier, which offers high gain with reduced power consumption and excellent linearity. In comparison to conventional cascode OTA, it achieves approximately 30 % power savings while maintaining the same level of linearity. To address the limited output swing of the cascode OTA, the finite impulse response (FIR) DAC technique, which is widely used in CTDSM, is introduced in the DTDSM. The FIR DAC output resembles that of a multibit DAC without requiring a mismatch shaping circuit. By incorporating FIR DAC, we effectively scale up integrator coefficients and decrease power consumption of the first-stage integrator. A prototype was fabricated in a 0.18-mu m CMOS process with an active area of 0.2 mm2, achieving peak SNDR/DR values of 94.5 and 96.5 dB while consuming only 190 mu W of power.
Keyword ：
Analog -to -digital converter (ADC) Analog -to -digital converter (ADC) Assisted OTA Assisted OTA Delta -sigma modulator Delta -sigma modulator Finite impulse response Finite impulse response Floating inverter amplifier Floating inverter amplifier
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| GB/T 7714 | Huang, Gongxing , Wei, Cong , Wei, Rongshan . A 94.5-dB SNDR 96.5-dB DR discrete-time delta-sigma modulator using FIA assisted OTA and FIR DAC feedback [J]. | MICROELECTRONICS JOURNAL , 2024 , 150 . |
| MLA | Huang, Gongxing et al. "A 94.5-dB SNDR 96.5-dB DR discrete-time delta-sigma modulator using FIA assisted OTA and FIR DAC feedback" . | MICROELECTRONICS JOURNAL 150 (2024) . |
| APA | Huang, Gongxing , Wei, Cong , Wei, Rongshan . A 94.5-dB SNDR 96.5-dB DR discrete-time delta-sigma modulator using FIA assisted OTA and FIR DAC feedback . | MICROELECTRONICS JOURNAL , 2024 , 150 . |
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The next-generation computing system is required to perform 10(18) floating point operations per second to address the exponential growth of data from sensory terminals, driven by advancements in artificial intelligence and the Internet of Things. Even if a supercomputer possesses the capability to execute these operations, managing heat dissipation becomes a significant challenge when the electronic synapse array reaches a comparable scale with the human neuron network. One potential solution to address thermal hotspots in electronic devices is the use of vertically-aligned hexagonal boron nitride (h-BN) known for its high thermal conductivity. In this study, we have developed textured h-BN films using the high power impulse magnetron sputtering technique. The thermal conductivity of the oriented h-BN film is approximately 354% higher than that of the randomly oriented counterpart. By fabricating electronic synapses based on the textured h-BN thin film, we demonstrate various bio-synaptic plasticity in this device. Our results indicate that orientation engineering can effectively enable h-BN to function as a suitable self-heat dissipation layer, thereby paving the way for future wearable memory devices, solar cells, and neuromorphic devices.
Keyword ：
boron nitride boron nitride high thermal conductivity high thermal conductivity low-power memory low-power memory neuromorphic computing neuromorphic computing vertically-aligned vertically-aligned
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| GB/T 7714 | Zhang, Haizhong , Ju, Xin , Jiang, Haitao et al. Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor [J]. | SCIENCE CHINA-MATERIALS , 2024 , 67 (6) : 1907-1914 . |
| MLA | Zhang, Haizhong et al. "Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor" . | SCIENCE CHINA-MATERIALS 67 . 6 (2024) : 1907-1914 . |
| APA | Zhang, Haizhong , Ju, Xin , Jiang, Haitao , Yang, Dan , Wei, Rongshan , Hu, Wei et al. Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor . | SCIENCE CHINA-MATERIALS , 2024 , 67 (6) , 1907-1914 . |
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This paper proposes a pseudo third-order discrete-time delta-sigma modulator to address the bottleneck of high resolution and low power consumption in Internet of Things (IoT) sensors. This architecture embeds a first-order passive noise-shaping SAR (Successive Approximation Register) quantizer into a conventional second-order delta-sigma modulator to achieve stronger noise-shaping capabilities. This allows the system to achieve higher peak SQNR (Signal-to-Quantizing Noise Ratio) at lower OSR (Over Sampling Ratio), effectively mitigating the design trade-off between system accuracy and power consumption, while reducing the use of active integrators. In response to the high power consumption of traditional active adders and the attenuation uncertainty of passive adders, this paper proposes a novel feedforward sum quantization circuit. It has the advantage of being insensitive to attenuation and reduces the driving pressure of the second stage active integrator, which further reduces the power consumption of the system. The proposed delta-sigma modulator is manufactured and tested using a 180 nm CMOS (Complementary Metal Oxide Semiconductor) process. At a power supply voltage of 1.4 V, the tested power consumption of the chip is 47.2 μW. With a bandwidth of 8 kHz, the DR (Dynamic Range), peak SNDR (Signal-to-Noise and Distortion Ratio), and SFDR (Spurious-Free Dynamic Range) of the modulator are 97.2 dB, 96.6 dB, and 114.4 dB, respectively. Therefore, figure-of-merit (FoM) Schreier and Walden for SNDR are 178.9 dB and 0.053 pJ/step. The pseudo third-order delta-sigma modulator proposed in this article achieves a good balance between power consumption and resolution, providing a good solution for low-power and high-resolution modulator design in the field of the IoTs. © 2024 Chinese Institute of Electronics. All rights reserved.
Keyword ：
delta-sigma modulator delta-sigma modulator high resolution high resolution internet of things internet of things low power low power
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| GB/T 7714 | Wei, C. , Huang, L.-J. , Hu, W. et al. Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors; [一种应用于物联网传感器的伪三阶Delta-Sigma 调制器] [J]. | Acta Electronica Sinica , 2024 , 52 (6) : 2123-2130 . |
| MLA | Wei, C. et al. "Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors; [一种应用于物联网传感器的伪三阶Delta-Sigma 调制器]" . | Acta Electronica Sinica 52 . 6 (2024) : 2123-2130 . |
| APA | Wei, C. , Huang, L.-J. , Hu, W. , Wei, R.-S. . Pseudo Third-Order Delta-Sigma Modulator Applied to Internet of Things Sensors; [一种应用于物联网传感器的伪三阶Delta-Sigma 调制器] . | Acta Electronica Sinica , 2024 , 52 (6) , 2123-2130 . |
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针对物联网传感器难以同时满足高分辨率与低功耗的瓶颈问题，本文设计了一种伪三阶离散时间delta-sigma调制器.该架构将一阶无源噪声整形SAR(Successive Approximation Register)量化器嵌入传统二阶delta-sigma调制器以实现更强的噪声整形能力.本文设计允许系统在更低的过采样率（Over Sampling Ratio,OSR）下获取更高的峰值SQNR(Signal-to-Quantizing Noise Ratio)，有效缓解了系统精度和功耗之间的设计矛盾，并且减少了有源积分器的使用.针对传统有源加法器高功耗和无源加法器存在衰减不确定性的问题，本文提出了一种新型前馈求和量化电路，它具有对衰减不敏感的优势并且降低了第二级有源积分器的驱动压力，这进一步降低了系统的功耗.本文提出的delta-sigma调制器采用180 nm CMOS(Complementary Metal Oxide Semiconductor)工艺制造并测试.在电源电压1.4 V下，芯片测试功耗为47.2μW.在带宽为8 kHz的测试条件下，调制器的DR(Dynamic Range)、峰值SNDR(Signal-to-Noise and Distortion Ratio)和SFDR(Spurious-Free Dynamic Range)分别为97.2 dB,96.6 dB和114.4 dB.因此，Schreier和Walden的SNDR FoM(Figure of Merit)优值达到了178.9 dB和0.053 pJ/step.本文提出的伪三阶delta-sigma调制器在功耗和分辨率之间实现了较好的权衡，为物联网领域的低功耗高分辨率调制器设计提供了较好的解决方案.
Keyword ：
delta-sigma调制器 delta-sigma调制器 低功耗 低功耗 物联网 物联网 高分辨率 高分辨率
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| GB/T 7714 | 魏聪 , 黄黎杰 , 胡炜 et al. 一种应用于物联网传感器的伪三阶Delta-Sigma调制器 [J]. | 电子学报 , 2024 , 52 (06) : 2123-2130 . |
| MLA | 魏聪 et al. "一种应用于物联网传感器的伪三阶Delta-Sigma调制器" . | 电子学报 52 . 06 (2024) : 2123-2130 . |
| APA | 魏聪 , 黄黎杰 , 胡炜 , 魏榕山 . 一种应用于物联网传感器的伪三阶Delta-Sigma调制器 . | 电子学报 , 2024 , 52 (06) , 2123-2130 . |
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Significant advancements in artificial neural networks (ANNs) have driven the rapid progress of artificial intelligence and machine learning. While current feedforward neural networks primarily handle static data, recurrent neural networks (RNNs) are designed for dynamical systems. However, RNNs demand extensive training on specific tasks, limiting their scalability and affordability for edge computing. Physical reservoir computing (RC) offers an alternative approach by mapping inputs into high-dimensional states, allowing for pattern analysis within a fixed reservoir. Unlike RNNs, RC is well-suited for temporal and sequential data processing with rapid speed and low training costs. This makes RC suitable for hardware implementation across various research domains. Nonetheless, existing demonstrations of RC remain constrained to small-scale device arrays. As electronic synapse arrays aim to approach very large-scale and highly complex hardware as in the human brain, managing heat dissipation becomes a formidable challenge. In this work, we successfully developed the neuristors based on textured h-BN films, prepared using a CMOS-compatible technique, and constructed a physical RC system based on as-fabricated devices. Our approach leverages vertically aligned BN to provide aligned diffusion paths for the reproducible migration process of metal ions from the electrodes and offers a potential solution for thermal management in electronic devices. This achievement highlights the promising potential of our neuristors for future high-density and energy-efficient neuromorphic computing.
Keyword ：
Boron nitride Boron nitride Highly textured Highly textured High thermal conductivity High thermal conductivity Neuromorphic device Neuromorphic device Reservoir computing Reservoir computing
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| GB/T 7714 | Zhang, Haizhong , Li, Jiayi , Ju, Xin et al. Highly textured CMOS-compatible hexagonal boron nitride-based neuristor for reservoir computing [J]. | CHEMICAL ENGINEERING JOURNAL , 2024 , 498 . |
| MLA | Zhang, Haizhong et al. "Highly textured CMOS-compatible hexagonal boron nitride-based neuristor for reservoir computing" . | CHEMICAL ENGINEERING JOURNAL 498 (2024) . |
| APA | Zhang, Haizhong , Li, Jiayi , Ju, Xin , Jiang, Jie , Wu, Jing , Chi, Dongzhi et al. Highly textured CMOS-compatible hexagonal boron nitride-based neuristor for reservoir computing . | CHEMICAL ENGINEERING JOURNAL , 2024 , 498 . |
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