This　paper　presents　a　low-power,　high-gain　integrator　design　that　uses　a　cascode　operational　transconductance　amplifier　(OTA)　with　floating　inverter-amplifier　(FIA)　assistance.　Compared　to　a　traditional　cascode,　the　proposed　integrator　can　achieve　a　gain　of　80　dB,　while　reducing　power　consumption　by　30%.　Upon　completing　the　analysis,　the　value　of　the　FIA　drive　capacitor　and　clock　scheme　for　the　FIA-assisted　OTA　were　obtained.　To　enhance　the　dynamic　range　(DR)　and　mitigate　quantization　noise,　a　tri-level　quantizer　was　employed.　The　design　of　the　feedback　digital-to-analog　converter　(DAC)　was　simplified,　as　it　does　not　use　additional　mismatch　shaping　techniques.　A　third-order,　discrete-time　delta-sigma　modulator　was　designed　and　fabricated　in　a　0.18　mu　m　complementary　metal-oxide　semiconductor　(CMOS)　process.　It　operated　on　a　1.8　V　supply,　consuming　221　mu　W　with　a　24　kHz　bandwidth.　The　measured　SNDR　and　DR　were　90.9　dB　and　95.3　dB,　respectively.