This　paper　presents　a　low-power　capacitive-to-digital　converter　(CDC)　based　on　incremental　delta-sigma　modulator.　It　utilizes　a　zoom-in　sensing　capacitor　that　is　insensitive　to　parasitic　capacitance,　improving　the　capacitance　resolution.　The　use　of　a　high-gain,　PVT-robust　current-starved　OTA　and　a　dynamic　bias　comparator　enhances　the　efficiency　of　the　system.　An　ultra-low-power　bias　circuit　is　integrated　into　the　system,　further　improving　integration　and　efficiency.　The　proposed　CDC　is　fabricated　using　a　180　nm　CMOS　process.　Operating　at　a　1.2　V　supply　voltage　and　a　250　kHz　sampling　frequency.　With　a　measurement　time　of　0.8　ms,　the　capacitance　resolution　is　107.6　aF,　and　the　power　consumption　is　10.27　mu　W.　The　figure-of-merits　(FoM)　is　2.06　pJ/step.