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Abstract：
Magnetic random-access memory (MRAM)-based computing-in-memory (CIM) schemes can be divided into write-based CIM and read-based CIM. Compared with read-based CIM, the write-based CIM can perform more operations such as AND, OR, majority (MAJ) gate, and full adder (FA). However, write-based CIM schemes require a large number of memory cells and multiple processing cycles. In this paper, we proposed a compact write-based CIM scheme by using a one transistor one high-speed switch magnetic tunnel junction (IT-IHSS-MTJ) memory cell to implement NAND, NOR, XOR, and MAJ gates within two write cycles and one read cycle. Moreover, we also demonstrated that FA operation can also be performed using three 1 T-IHSS-MTJ cells within six cycles. According to the simulation results performed using the SMIC 40 nm CMOS process and the HSS-MTJ SPICE model, we have demonstrated that these logic functions can be achieved. When compared to the write-based CIM using SOT-MRAM, the proposed CIM requires fewer cells and shorter latency to achieve the same logic operations. © 2024 IEEE.
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Year： 2024
Page： 666-670
Language： English
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