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author:

Renping, Wang (Renping, Wang.) [1] (Scholars:王仁平) | Tingting, Zhuang (Tingting, Zhuang.) [2] | Hao, Jiang (Hao, Jiang.) [3]

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EI Scopus

Abstract:

In this paper, we proposed a 32-bit improved adder combined with sparse tree by radix-2 and carry select. We designed its models-point operation, carry-out, 4-bit ripple-carry adder and 4-bit selector by reversible logic, and designed with smic0.18um process corresponding MOS circuit to achieve. The simulation results could verify that the algorithm and the design by reversible logic are right. © 2016 IEEE.

Keyword:

Adders Carry logic Computer circuits Forestry Logic gates

Community:

  • [ 1 ] [Renping, Wang]Department of Microelectronics Science and Engineering, Fuzhou University, Fuzhou, Fujian; 350116, China
  • [ 2 ] [Tingting, Zhuang]Department of Microelectronics Science and Engineering, Fuzhou University, Fuzhou, Fujian; 350116, China
  • [ 3 ] [Hao, Jiang]Department of Microelectronics Science and Engineering, Fuzhou University, Fuzhou, Fujian; 350116, China

Reprint 's Address:

  • 江浩

    [hao, jiang]department of microelectronics science and engineering, fuzhou university, fuzhou, fujian; 350116, china

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Year: 2016

Language: English

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ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 7

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