In　this　study,　we　present　a　threshold　logic　gate　based　implementation　of　a　(7,　3)　counter　using　Singleelectron　Transistor　(SET)　and　Mtal-oxide-Semiconductor　(MOS)　transistor.　The　unique　properties　of　the　SET/MOS　hybrid　circuit　are　exploited　in　the　realization　of　power　and　area　efficient　threshold　logic　gates.　It　is　merely　composed　of　three　threshold　logic　gates　and　two　inverters.　The　total　device　count　is　substantially　reduced　to　13,　i.e.　5　PMOS　transistors,　5　NMOS　transistors,　and　3　SETs,　while　the　conventional　Boolean　logic　gate　based　(7,　3)　counter　designed　only　by　MOS　transistors　consumes　nearly　194　devices.　Moreover,　the　power　consumption　of　the　proposed　(7,　3)　counter　is　only　6.92　nW.　The　correctness　of　the　proposed　circuit　is　verified　through　HSPICE　simulation.　Simulation　results　show　that　the　proposed　(7,　3)　counter　is　superior　to　the　Boolean　logic　gate　based　CMOS　one　in　terms　of　circuit　complexity　and　area　efficiency.　These　features　make　the　proposed　(7,　3)　counter　very　attractive　in　the　applications　of　multiplier　circuits　and　other　high　density　and　high　performance　digital　circuits.　©　Maxwell　Scientific　Organizational,　2012.