In　recent　years,　the　resolution　and　frame　rate　of　video　have　been　continuously　improved　to　meet　people’s　increasing　demand　for　video　data.　However,　the　compression　encoding　speed　of　real-time　video　sequence　is　often　restricted　by　frame　rate　and　resolution.　The　higher　the　frame　rate　and　resolution　are,　the　longer　the　encoding　time　will　be.　In　order　to　achieve　real-time　compression　encode　for　video　sequences　with　higher　resolution　and　frame　rate,　this　paper　designed　a　new　parallel　pipeline　hardware　architecture　of　intra　rate-distortion　optimization　prediction　mode,　which　supports　intra　prediction　coding　of　up　to　64×64　coding　tree　unit.　Firstly,　a　parallel　scheme　with　9-way　prediction　mode　was　designed.　Secondly,　a　pipeline　hardware　architecture　was　implemented　based　on　a　4×4　block　as　the　basic　processing　unit　in　a　Z-shaped　scanning　order,　and　the　prediction　data　of　32×32　prediction　units　were　reused　to　replace　the　prediction　data　of　64×64　prediction　units　so　as　to　reduce　the　amount　of　calculation.　Lastly,　a　new　Hadamard　transform　circuit　was　proposed　based　on　this　pipelined　architecture　for　efficient　pipelined　processing.　The　experimental　results　show　that:　on　the　Altera　Arria　10　series　field　programmable　gate　array,　the　9-way　mode　parallel　architecture　only　occupies　75　kb　look　up　table　and　55　kb　register　resources,　the　main　frequency　can　reach　207　MHz,　and　it　only　takes　4　096　clocks　cycles　to　complete　a　64×64　coding　tree　unit　prediction　and　can　support　real-time　encoding　of　1　080　P　resolution　99　f/s　full　I-frame　at　most.　Compared　with　the　existing　design　scheme,　the　scheme　designed　in　this　paper　can　realize　higher　frame　rate　1080P　real　time　video　encoding　with　smaller　circuit　area.　©　2023　South　China　University　of　Technology.　All　rights　reserved.