Special　accelerator　architecture　has　achieved　great　success　in　processor　architecture,　and　it　is　trending　in　computer　architecture　development.　However,　as　the　memory　access　pattern　of　an　accelerator　is　relatively　complicated,　the　memory　access　performance　is　relatively　poor,　limiting　the　overall　performance　improvement　of　hardware　accelerators.　Moreover,　memory　controllers　for　hardware　accelerators　have　been　scarcely　researched.　We　consider　that　a　special　accelerator　memory　controller　is　essential　for　improving　the　memory　access　performance.　To　this　end,　we　propose　a　dynamic　random　access　memory　(DRAM)　memory　controller　called　NNAMC　for　neural　network　accelerators,　which　monitors　the　memory　access　stream　of　an　accelerator　and　transfers　it　to　the　optimal　address　mapping　scheme　bank　based　on　the　memory　access　characteristics.　NNAMC　includes　a　stream　access　prediction　unit　(SAPU)　that　analyzes　the　type　of　data　stream　accessed　by　the　accelerator　via　hardware,　and　designs　the　address　mapping　for　different　banks　using　a　bank　partitioning　model　(BPM).　The　image　mapping　method　and　hardware　architecture　were　analyzed　in　a　practical　neural　network　accelerator.　In　the　experiment,　NNAMC　achieved　significantly　lower　access　latency　of　the　hardware　accelerator　than　the　competing　address　mapping　schemes,　increased　the　row　buffer　hit　ratio　by　13.68%　on　average　(up　to　26.17%),　reduced　the　system　access　latency　by　26.3%　on　average　(up　to　37.68%),　and　lowered　the　hardware　cost.　In　addition,　we　also　confirmed　that　NNAMC　efficiently　adapted　to　different　network　parameters.