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学者姓名：陈传东
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Abstract ：
The Ordered Escape Routing (OER) problem, which is an NP-hard problem, is critical to PCB design. Primary methods based on integer linear programming (ILP) work well on small-scale PCBs with fewer pins. However, when dealing with large-scale instances, traditional ILP strategies frequently cause time violations as the number of variables increases due to time-consuming preprocessing. In addition, heuristic algorithms have a time advantage when dealing with specific problems. In this paper, We propose an efficient two-stage escape routing method that employs LP for global routing and uses a heuristic algorithm to deal with the path intersection problem to minimize wiring length and runtime for large-scale PCBs. We first model the OER problem as a min-cost multi-commodity flow problem and use ILP to solve it. Then, we relax the non-crossing constraints and transform the ILP model into an LP model to reduce the runtime. we also construct a crossing graph according to the intersection of routing paths and propose a heuristic algorithm to locate congestion quickly. Finally, we reduce the local area capacity and allow global automatic congestion optimization. Compared with the state-of-the-art work, experimental results show that our method can reduce the routing time by 60% and handle larger-scale PCB escape routing problems.
Keyword ：
Heuristic algorithm Heuristic algorithm Linear programming Linear programming Min-cost multi-commodity flow Min-cost multi-commodity flow Ordered escape routing Ordered escape routing
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| GB/T 7714 | Lin, Disi , Chen, Chuandong , Wei, Rongshan et al. Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB [J]. | INTEGRATION-THE VLSI JOURNAL , 2025 , 100 . |
| MLA | Lin, Disi et al. "Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB" . | INTEGRATION-THE VLSI JOURNAL 100 (2025) . |
| APA | Lin, Disi , Chen, Chuandong , Wei, Rongshan , Liu, Qinghai , He, Huan , Zhu, Ziran et al. Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB . | INTEGRATION-THE VLSI JOURNAL , 2025 , 100 . |
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As the feature sizes keep shrinking, interconnect delays have become a major limiting factor for FPGA timing closure. Traditional placement algorithms that address wirelength alone are no longer sufficient to close timing, especially for the large-scale heterogeneous FPGAs. In this paper, we propose an analytical placement algorithm for FPGA timing optimization. By leveraging the look-up table technique, we first present a smoothed routing-architecture-aware timing model to calculate each connection delay rapidly. Then, an effective wirelength and timing co-optimization strategy is developed to produce high-quality placements without timing violations. Finally, a delay optimal region-based detail placement strategy is designed to further improve the timing performance. Compared with Vivado 2023.1 on AMD benchmark suites for xc7k325t device, experimental results show that our algorithm achieves not only a 3.2% improvement in worst slack, but also a 2.5% reduction for routed wirelength.
Keyword ：
Field programmable gate arrays Field programmable gate arrays Physical design Physical design Placement Placement Timing optimization Timing optimization
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| GB/T 7714 | Lin, Zhifeng , Chen, Yilu , Xie, Yanyue et al. An analytical timing-driven placer for modern heterogeneous FPGAs [J]. | JOURNAL OF SUPERCOMPUTING , 2025 , 81 (1) . |
| MLA | Lin, Zhifeng et al. "An analytical timing-driven placer for modern heterogeneous FPGAs" . | JOURNAL OF SUPERCOMPUTING 81 . 1 (2025) . |
| APA | Lin, Zhifeng , Chen, Yilu , Xie, Yanyue , Chen, Chuandong , Yu, Jun , Chen, Jianli . An analytical timing-driven placer for modern heterogeneous FPGAs . | JOURNAL OF SUPERCOMPUTING , 2025 , 81 (1) . |
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Printed circuit board (PCB) placement is a critical stage in industrial chip design, which still heavily relies on manual methods, leading to substantial design time consumption. Given the frequent occurrence of similar or identical modules in different PCB designs, the reuse of placements emerges as a promising avenue to enhance the efficiency of PCB placement. In this paper, we propose a subgraph matching based reference placement algorithm to achieve PCB placement reuse, thereby improving placement efficiency. We first take the netlist of the already placed and unplaced circuits as input and abstract them into graphs. Then, we construct and filter candidate spaces based on the characteristics of components and nets. In the process of filtering candidate spaces, we adopt diversity handling that includes cut edges and block nodes to ensure the proposed algorithm can handle inexact matching. Finally, we introduce virtual nodes to construct a matching tree using a combination of depth-first search (DFS) and breadth-first search (BFS), and then perform hierarchical matching based on this matching tree to complete the subgraph matching and obtain the placement results. Experimental results show that in large-scale PCB cases, our algorithm runs much faster than the state-of-the-art works. Particularly, the matching rate of our algorithm is almost 100% for the tested cases.
Keyword ：
PCB PCB placement placement subgraph matching subgraph matching
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| GB/T 7714 | Chen, Chuandong , Lin, Haiming , Su, Miaodi et al. Subgraph Matching with Diversity Handling and Its Applications to PCB Placement [J]. | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 , 2024 : 468-473 . |
| MLA | Chen, Chuandong et al. "Subgraph Matching with Diversity Handling and Its Applications to PCB Placement" . | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 (2024) : 468-473 . |
| APA | Chen, Chuandong , Lin, Haiming , Su, Miaodi , He, Huan , Chen, Jianli , Zhu, Ziran . Subgraph Matching with Diversity Handling and Its Applications to PCB Placement . | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 , 2024 , 468-473 . |
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Legalized routing is an essential part of PCB automatic routing. It solves the problem of wiring conflicts and obtains routing results that comply with the constraints of design rules. Traditional legalized routing problems mostly use trial backtracking methods, but with increasing design complexity and design rules, avoiding wiring conflicts between networks has become increasingly challenging. This paper proposes a legalized routing algorithm based on linear programming to obtain the optimal wiring trajectory under specified topological constraints. First, the corresponding routing model was established based on numerous routing rules, and a routing grid diagram was found using obstacles as grid points. Secondly, a global routing algorithm was used to obtain the estimated wiring path, and integer linear programming was used to realize the mathematical modeling of the legalized routing problem. Finally, a multi-line simultaneous routing strategy was used to design and implement a detailed routing algorithm, optimizing the routing results. We use C++ to complete the coding work and thoroughly test the PCB use cases of different sizes. The experimental results show that our algorithm still maintains a 100% routing success rate, good time performance, and excellent routing quality with large-scale use cases compared with the trial backtracking method.
Keyword ：
detailed algorithm detailed algorithm escape routing escape routing integer linear programming integer linear programming printed circuit board printed circuit board
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| GB/T 7714 | Chen, Chuandong , Tong, Xin , Liu, Qinghai et al. Legalized Routing Algorithm Based on Linear Programming [J]. | ELECTRONICS , 2023 , 12 (20) . |
| MLA | Chen, Chuandong et al. "Legalized Routing Algorithm Based on Linear Programming" . | ELECTRONICS 12 . 20 (2023) . |
| APA | Chen, Chuandong , Tong, Xin , Liu, Qinghai , Chen, Jiarui , Lin, Zhifeng . Legalized Routing Algorithm Based on Linear Programming . | ELECTRONICS , 2023 , 12 (20) . |
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有序逃逸布线问题作为PCB设计中的关键一环,属于一类特殊的NP-困难问题,近年来得到广泛研究.传统方法中,基于整数线性规划或者是拆线重布类的启发式算法只适用于引脚数目较少的PCB引脚阵列,否则容易出现时间违规而导致布线失败.针对传统方法中大规模全局自动布线难的问题,基于线性规划的全局自动布线算法提出采用线性规划解决逃逸布线问题,并提出降低线网容量化解拥塞的新方法.与最新的逃逸布线算法相比,在处理大规模问题时,该算法不仅可以实现全部引脚的有序逃逸,并且布线时间提升50％,节省31％线长.
Keyword ：
PCB自动布线 PCB自动布线 拥塞驱动 拥塞驱动 有序逃逸 有序逃逸 线性规划 线性规划
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| GB/T 7714 | 陈虹 , 陈传东 , 魏榕山 . 一种基于线性规划的全局逃逸布线算法 [J]. | 电子技术应用 , 2023 , 49 (1) : 97-101 . |
| MLA | 陈虹 et al. "一种基于线性规划的全局逃逸布线算法" . | 电子技术应用 49 . 1 (2023) : 97-101 . |
| APA | 陈虹 , 陈传东 , 魏榕山 . 一种基于线性规划的全局逃逸布线算法 . | 电子技术应用 , 2023 , 49 (1) , 97-101 . |
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逃逸布线是印刷电路板设计的一个重要组成部分.针对并行逃逸布线的方法用于较大规模电路板布线时速度慢且结果不够好的问题,该文提出一种结合改进A*算法与拆线重布的有序逃逸布线方法.首先,通过代价预估函数确定引脚的布线顺序,使用改进A*算法初始化有序逃逸布线.接着,优化同长度布线路径,调整拥挤区域布线路径.最后,使用A*算法和广度优先搜索进行拆线重布.实验结果表明,该方法对给出的所有测试用例都实现了100％的逃逸,得到有序逃逸路径的可行解非常接近最优解,CPU时间比布尔可满足性问题(SAT)算法与最小费用多商品流(MMCF)算法平均减少分别约为95.6％,?97.8％,总体线长也接近最优.提出的方法能够明显减少寻找可行解的时间,提高布线质量.
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| GB/T 7714 | 邓新国 , 叶似锦 , 陈家瑞 et al. 结合改进A*算法与拆线重布的有序逃逸布线 [J]. | 电子与信息学报 , 2021 , 43 (6) : 1609-1616 . |
| MLA | 邓新国 et al. "结合改进A*算法与拆线重布的有序逃逸布线" . | 电子与信息学报 43 . 6 (2021) : 1609-1616 . |
| APA | 邓新国 , 叶似锦 , 陈家瑞 , 陈传东 . 结合改进A*算法与拆线重布的有序逃逸布线 . | 电子与信息学报 , 2021 , 43 (6) , 1609-1616 . |
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Abstract ：
逃逸布线是印刷电路板设计的一个重要组成部分。针对并行逃逸布线的方法用于较大规模电路板布线时速度慢且结果不够好的问题,该文提出一种结合改进A~*算法与拆线重布的有序逃逸布线方法。首先,通过代价预估函数确定引脚的布线顺序,使用改进A~*算法初始化有序逃逸布线。接着,优化同长度布线路径,调整拥挤区域布线路径。最后,使用A~*算法和广度优先搜索进行拆线重布。实验结果表明,该方法对给出的所有测试用例都实现了100%的逃逸,得到有序逃逸路径的可行解非常接近最优解,CPU时间比布尔可满足性问题(SAT)算法与最小费用多商品流(MMCF)算法平均减少分别约为95.6%, 97.8%,总体线长也接近最优。提出的...
Keyword ：
A~*算法 A~*算法 拆线重布 拆线重布 最短路径 最短路径 有序逃逸布线 有序逃逸布线
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| GB/T 7714 | 邓新国 , 叶似锦 , 陈家瑞 et al. 结合改进A~*算法与拆线重布的有序逃逸布线 [J]. | 电子与信息学报 , 2021 , 43 (06) : 1609-1616 . |
| MLA | 邓新国 et al. "结合改进A~*算法与拆线重布的有序逃逸布线" . | 电子与信息学报 43 . 06 (2021) : 1609-1616 . |
| APA | 邓新国 , 叶似锦 , 陈家瑞 , 陈传东 . 结合改进A~*算法与拆线重布的有序逃逸布线 . | 电子与信息学报 , 2021 , 43 (06) , 1609-1616 . |
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Special accelerator architecture has achieved great success in processor architecture, and it is trending in computer architecture development. However, as the memory access pattern of an accelerator is relatively complicated, the memory access performance is relatively poor, limiting the overall performance improvement of hardware accelerators. Moreover, memory controllers for hardware accelerators have been scarcely researched. We consider that a special accelerator memory controller is essential for improving the memory access performance. To this end, we propose a dynamic random access memory (DRAM) memory controller called NNAMC for neural network accelerators, which monitors the memory access stream of an accelerator and transfers it to the optimal address mapping scheme bank based on the memory access characteristics. NNAMC includes a stream access prediction unit (SAPU) that analyzes the type of data stream accessed by the accelerator via hardware, and designs the address mapping for different banks using a bank partitioning model (BPM). The image mapping method and hardware architecture were analyzed in a practical neural network accelerator. In the experiment, NNAMC achieved significantly lower access latency of the hardware accelerator than the competing address mapping schemes, increased the row buffer hit ratio by 13.68% on average (up to 26.17%), reduced the system access latency by 26.3% on average (up to 37.68%), and lowered the hardware cost. In addition, we also confirmed that NNAMC efficiently adapted to different network parameters.
Keyword ：
address mapping address mapping DRAM DRAM memory access optimization memory access optimization memory controller memory controller
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| GB/T 7714 | Wei, Rongshan , Li, Chenjia , Chen, Chuandong et al. Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller [J]. | ELECTRONICS , 2021 , 10 (4) . |
| MLA | Wei, Rongshan et al. "Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller" . | ELECTRONICS 10 . 4 (2021) . |
| APA | Wei, Rongshan , Li, Chenjia , Chen, Chuandong , Sun, Guangyu , He, Minghua . Memory Access Optimization of a Neural Network Accelerator Based on Memory Controller . | ELECTRONICS , 2021 , 10 (4) . |
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Resistive random access memory device (RRAM) has been widely used in various novel circuit systems, such as memory, artificial intelligence, and neural networks, due to its unique memory characteristics. However, there are very few studies focusing on analytic modeling of RRAM. In this article, modeling for solving analytic approximate solution to the state variable of RRAM, based on the proposed Multistage Homotopy Analysis Method (MuHAM), is proposed. Different from traditional HAM, the time span under consideration is divided into many subintervals, then the convergence control parameter in each subinterval is optimized to achieve high approximation accuracy. By simulating and comparing the obtained analytic solutions with solutions solved by other traditional homotopy-based modeling methodologies and by numerical analyses, we verified that MuHAM has higher Quality Factor (introduced to evaluate the model accuracy and computational cost comprehensively), hence improving the simulation efficiency. Besides the classical Hewlett-Packard (HP) RRAM, some current RRAMs are also verified. MuHAM also has the advantages of enabling both qualitative and quantitative analyses, and immunity to convergence issues. It is particularly suitable for the analytic modeling of the other novel memory devices having strong nonlinearity.
Keyword ：
analytic modeling analytic modeling high accuracy high accuracy multistage homotopy analysis method (MuHAM) multistage homotopy analysis method (MuHAM) Resistive random access memory device (RRAM) Resistive random access memory device (RRAM)
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| GB/T 7714 | Hu, Wei , Luo, Haibo , Chen, Chuandong et al. Analytic Modeling for RRAM Based on Multistage Homotopy Analysis Method [J]. | IEEE TRANSACTIONS ON NANOTECHNOLOGY , 2020 , 19 : 179-191 . |
| MLA | Hu, Wei et al. "Analytic Modeling for RRAM Based on Multistage Homotopy Analysis Method" . | IEEE TRANSACTIONS ON NANOTECHNOLOGY 19 (2020) : 179-191 . |
| APA | Hu, Wei , Luo, Haibo , Chen, Chuandong , Wei, Rongshan . Analytic Modeling for RRAM Based on Multistage Homotopy Analysis Method . | IEEE TRANSACTIONS ON NANOTECHNOLOGY , 2020 , 19 , 179-191 . |
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High precision and smart sensors make up an indispensable data entry for the Internet of Things technology. Nonetheless, conventional calibration algorithms mainly implemented on the software, such as least squares, polynomial fitting, and interpolation, exhibit limited calibration accuracy that does not reflect a real-time measurement of the sensors. The problem can be resolved with an MCU-based sensor calibration system proposed herein, which mainly employs particle swarm optimization (PSO)-back propagation (BP) neural network. The system firstly reads sensor data through l2C bus and then uses the BP neural network and PSO algorithm to automatically calibrate these data in real time. Sigmoid activation function was implemented via a piecewise polynomial fitting to create a trade-off between hardware resource and precision. A performance test conducted on temperature sensors showed a maximum error of 0.16 degrees C within the measurement range of -40-100 degrees C with three times the standard deviation (3 sigma) error of +/- 0.23 degrees C and overall linearity of 0.1143% after the calibration system was added as compared to the significantly higher error of +/- 0.63 degrees C without the calibration. (C) 2019 Elsevier B.V. All rights reserved.
Keyword ：
High precision High precision MCU MCU PSO-BP neural network PSO-BP neural network Sensor calibration system Sensor calibration system
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| GB/T 7714 | Wei, Rongshan , Ouyang, Kui , Bao, Xiaotian et al. High-precision smart calibration system for temperature sensors [J]. | SENSORS AND ACTUATORS A-PHYSICAL , 2019 , 297 . |
| MLA | Wei, Rongshan et al. "High-precision smart calibration system for temperature sensors" . | SENSORS AND ACTUATORS A-PHYSICAL 297 (2019) . |
| APA | Wei, Rongshan , Ouyang, Kui , Bao, Xiaotian , Gao, Xiong , Chen, Chuandong . High-precision smart calibration system for temperature sensors . | SENSORS AND ACTUATORS A-PHYSICAL , 2019 , 297 . |
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