I　proposed　a　method　of　using　full-custom　design　32　×　32　multiplier　to　enhance　performance,　reduce　the　power　consumption　and　the　area　of　layout.　I　use　improved　Wallace　tree　structure　for　partial　product　compression,　truncated　beyond　the　64　part　of　the　plot　and　the　look-ahead　logarithmic　adder　using　Radix-4　Kogge-Stone　tree　algorithm　raise　the　multiplier　performance.　In　the　design　of　Booth2　encoding　circuit　and　compression　circuit,　I　use　a　transmission　gate　logic　design　with　higher　speed　and　smaller　area.　I　also　use　Euler　path　method　and　heuristic　Euler　path　method　to　reduce　the　layout　area.　The　design　use　SMIC　0.18μm　1P4M　CMOS　process,　with　a　layout　area　of　0.1684mm2.　In　a　large　number　of　test　patterns,　simulation　results　show　that　the　computation　time　of　a　32　×　32　multiplication　is　less　than　3.107ns.　©　(2013)　Trans　Tech　Publications,　Switzerland.