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In this paper, the degradation of drain-induced barrier lowering (DIBL) in FinFETs is experimentally studied under various hot carrier degradation (HCD) stress conditions. A test method is developed to characterize channel barrier height modulation under different HCD stress conditions. A linear relationship of ΔVthlin and ΔVthsat after HCD is found. Then a compact model of HCD-induced ΔDIBL is proposed. The results are helpful for the physical understanding and modeling of HCD in nanoscale FinFETs and aging-aware circuit design. © 2018 IEEE.
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Year: 2018
Language: English
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