Investigation of DIBL Degradation in Nanoscale FinFETs under Various Hot Carrier Stresses - Details

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In　this　paper,　the　degradation　of　drain-induced　barrier　lowering　(DIBL)　in　FinFETs　is　experimentally　studied　under　various　hot　carrier　degradation　(HCD)　stress　conditions.　A　test　method　is　developed　to　characterize　channel　barrier　height　modulation　under　different　HCD　stress　conditions.　A　linear　relationship　of　ΔV　thlin　and　ΔV　thsat　after　HCD　is　found.　Then　a　compact　model　of　HCD-induced　ΔDIBL　is　proposed.　The　results　are　helpful　for　the　physical　understanding　and　modeling　of　HCD　in　nanoscale　FinFETs　and　aging-aware　circuit　design.　©　2018　IEEE.

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[ 1 ] [Sun, Z.]College of Physics and Information Engineering, Fuzhou University, Fujian, 350002, China
[ 2 ] [Yu, Z.]Institute of Microelectronics, Peking University, Beijing, 100871, China
[ 3 ] [Wang, R.]Institute of Microelectronics, Peking University, Beijing, 100871, China
[ 4 ] [Zhang, J.]Institute of Microelectronics, Peking University, Beijing, 100871, China
[ 5 ] [Zhang, Z.]Institute of Microelectronics, Peking University, Beijing, 100871, China
[ 6 ] [Lu, P.]College of Physics and Information Engineering, Fuzhou University, Fujian, 350002, China
[ 7 ] [Huang, R.]Institute of Microelectronics, Peking University, Beijing, 100871, China

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2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2018 - Proceedings

Year： 2018

Language： English

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SCOPUS Cited Count： 4

ESI Highly Cited Papers on the List： 0 Unfold All

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