Discrete　cosine　transform　(DCT)　is　an　indispensable　module　in　video　codecs　and　is　a　major　part　in　many　video　coding　standards　including　the　latest　high　efficiency　video　coding　(HEVC).　As　the　video　resolution　increases,　both　transform　sizes　and　the　number　of　transforms　increase　continuously　which　poses　challenges　to　the　reusability　design　especially　in　hardware　implementation.　This　paper　presents　reconfigurable　transform　architecture　to　flexibly　support　the　reusability　of　different　transform　sizes.　The　proposed　architecture　maximally　reuses　the　hardware　resources　by　rearranging　the　order　of　input　data　for　different　transform　sizes　while　still　exploiting　the　butterfly　property.　Furthermore,　this　architecture　supports　reconfigurable　throughput　according　to　different　hardware　resource　requirements.　By　applying　the　proposed　architecture　to　the　field-programmable　gate　array　(FPGA)　design　of　HEVC　core　transform　matrices,　the　synthesis　results　show　much　lower　consumption　of　hardware　resources　comparing　to　existing　methods　in　the　literature.　The　implementation　in　Altera＇s　Stratix　III　FPGA　can　operate　at　139　MHz　and　supports　real-time　processing　of　$3840\times　2160$　ultra-high　definition　video　at　a　minimum　of　45　f/s　and　up　to　359　f/s　for　different　DCT　sizes.　©　1991-2012　IEEE.