FPGA design and implementation of low power consumption LDPC encoder based on DVB-S2 - Details

author：

Zou, Xingyu (Zou, Xingyu.) ^[1] | Qian, Hui (Qian, Hui.) ^[2] (Scholars：钱慧) | Cheng, Shuying (Cheng, Shuying.) ^[3] (Scholars：程树英)

Indexed by：

EI Scopus

Abstract：

According　to　DVB-S2　standard　for　LDPC　(Low　Density　Parity　Check)　codes,　a　novel　LDPC　codes　encoder　circuit　structure　is　designed.　The　design　has　been　implemented　on　the　FPGA　(Filed　Programmable　Gate　Array).　Simulations　results　show　that,　due　to　the　random　nature　of　the　input　data,　this　structure　significantly　reduces　the　power　consumption　of　the　calculation　circuit.　Meanwhile,　during　the　entire　coding　process,　the　data　is　processed　parallelly　and　distributed　storage　so　that　we　can　not　only　enhance　the　information　processing　rate　but　also　save　storage　space　in　FPGA.　©　2011　Springer-Verlag.

Keyword：

Codes (symbols) Digital storage Electric power utilization Field programmable gate arrays (FPGA) Integrated circuit design Signal encoding

Community：

[ 1 ] [Zou, Xingyu]School of Physics and Information Engineering, Institute of Micro-Nano Devices and Solar Cells, Fuzhou University, Fuzhou 350108, Fujian Province, China
[ 2 ] [Qian, Hui]School of Physics and Information Engineering, Institute of Micro-Nano Devices and Solar Cells, Fuzhou University, Fuzhou 350108, Fujian Province, China
[ 3 ] [Cheng, Shuying]School of Physics and Information Engineering, Institute of Micro-Nano Devices and Solar Cells, Fuzhou University, Fuzhou 350108, Fujian Province, China