At　first,　this　paper　analyzes　the　basic　structure　and　hardware　characteristics　of　the　FIR　digital　filter,　and　then　a　design　method　of　the　FIR　filter　is　discussed　on　the　basis　of　the　FIR　filter　structure.　It　is　a　method　that　is　based　on　FPGA,　draws　the　coefficient　by　Matlab　and　adopts　the　pipeline　to　implete　the　FIR　digital　filter　.　The　article　focuses　on　the　introduction　of　the　overall　framework　of　the　FIR　digital　filter　adopting　the　finitestate　machine　as　well　as　the　principle　of　each　module　of　the　design.　The　design　is　impleted　by　use　of　the　Verilog　hardware　description　language　and　each　module　is　verified　and　simulated　by　Quartus　8.0　and　Modelsim-Altera.　©2009　IEEE.