Indexed by：
Abstract：
Discrete Cosine Transform is widely used in image compression. This paper describes the FPGA implementation of a two dimensional (8×8) point Discrete Cosine Transform (8×8 point 2D-DCT) processor with Verilog HDL for application of image processing. The row-column decomposition algorithm and pipelining are used to produce the high quality circuit design with the max clock frequency of 318MHz when implemented in a Xinlinx VIRTEX-II PRO FPGA chip. © 2011 Springer-Verlag Berlin Heidelberg.
Keyword：
Reprint 's Address：
Email：
Version：
Source ：
ISSN： 1876-1100
Year： 2011
Issue： VOL. 1
Volume： 97 LNEE
Page： 633-639
Language： English
Cited Count：
WoS CC Cited Count： 0
SCOPUS Cited Count： 3
ESI Highly Cited Papers on the List： 0 Unfold All
WanFang Cited Count：
Chinese Cited Count：
30 Days PV： 2
Affiliated Colleges：
