In　this　paper,　we　present　a　new　data　structure　element　for　constructing　a　Huffman　tree,　and　a　new　algorithm　is　developed　to　improve　the　efficiency　of　Huffman　coding　by　constructing　the　Huffman　tree　synchronously　with　the　generation　of　codewords.　The　improved　algorithm　is　adopted　in　a　VLSI　architecture　for　a　Huffman　encoder.　The　VLSI　implementation　is　realized　using　the　Verilog　hardware　description　language　and　simulated　by　Modelsim.　The　proposed　scheme　achieves　rapid　coding　speed　with　a　gate　count　of　9.962　K　using　SMIC　0.18　micron　standard　library　cells.