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author:

周维 (周维.) [1] | 钱慧 (钱慧.) [2] (Scholars:钱慧) | 江浩 (江浩.) [3]

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CQVIP PKU CSCD

Abstract:

在分析基本FIR滤波器原理的基础上,设计了基于微程序的FIR滤波系统的硬件架构,并采用自顶向下的设计方法,利用硬件描述语言Verilog HDL实现了该系统,最后在Xilinx软件开发工具vivad02016.1上进行了仿真,并在Matlab软件中进行了验证.结果表明,设计的基于微程序的FIR滤波系统硬件架构可行,软件可靠,并具有阶数可扩展、可重构、可移植、占有资源少、功耗低的优点.

Keyword:

FIR滤波器 FPGA Verilog HDL 微指令 微程序

Community:

  • [ 1 ] [周维]福州大学
  • [ 2 ] [钱慧]福州大学
  • [ 3 ] [江浩]福州大学

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Source :

微电子学

ISSN: 1004-3365

CN: 50-1090/TN

Year: 2017

Issue: 3

Volume: 47

Page: 347-350,354

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count: -1

Chinese Cited Count:

30 Days PV: 3

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