This　paper　presents　a　novel　128-point　FFT　processor　developed　primarily　for　the　application　in　a　MB-OFDM　based　UWB　system,in　which　a　N=4*4*　4*2　algorithm　was　exploited.　A　radix-22　unit　and　a　radix-2　2　/2　unit　form　the　two-stage　pipelined　architecture.　The　parallel　butterfly　unit　enhances　the　processing　speed　efficiently.　Moreover,　a　unique　butterfly　both　shared　by　radix-22　and　radix-2　is　proposed　to　save　the　silicon　area.　The　feedback　loop　in　butterfly　units　is　used　to　avoid　storing　the　data　into　the　RAM　at　every　clock.　The　design　was　carried　out　in　the　SMIC　0.25-um　five-metal　layer　BiCMOS　technology.　Clock　rate　at　66M　Hz　has　been　achieved.　©　2006　IEEE.