This　paper　proposes　a　low　power　read-out　integrated　circuit　(ROIC)　for　multiple　sensors　having　a　DC　output　signal.　It　comprises　a　chopper-stabilized　instrumentation　amplifier　(CSIA)　followed　by　a　second-order　incremental　analog-to-digital　converter　(IADC).　The　CSIA　has　a　dual-frequency　path　to　effectively　eliminate　any　1/f　noise　and　offset.　A　variable　gain　module　(VGM)　is　also　connected　to　the　CSIA　to　improve　its　range　of　potential　applications.　A　CMOS　buffer　amplifier　followed　by　the　CSIA　is　used　to　achieve　the　ROIC＇s　linearity　and　drive　capability.　The　back-end　of　the　ROIC　has　a　switched-capacitor　IADC　to　provide　a　digital　output.　The　correlated　double　sampling　(CDS)　technique　was　used　in　the　IADC＇s　first　integrator　to　reduce　the　offset　and　noise.　The　combination　of　these　techniques　enables　the　ROIC　to　achieve　an　input　referred　offset　of　5　mu　V　and　a　best　error　voltage　of　+/-　0.01　mV.　The　ROIC　was　implemented　in　0.18　mu　m　CMOS　technology.　It　occupies　an　area　of　approximately　2.56　mm(2)　and　consumes　835　mu　A　of　current　from　a　1.6V　of　supply　voltage.