Routability　has　always　been　a　significant　challenge　in　Very　Large　Scale　Integration　(VLSI)　design.　To　overcome　the　potential　mismatch　between　the　global　routing　results　and　the　detailed　routing　requirements,　track　assignment　is　introduced　to　achieve　an　efficient　routability　estimation.　Moreover,　with　the　increasing　scale　of　circuits,　the　intricate　interconnections　among　the　components　on　the　chip　lead　to　increased　timing　delay　in　signal　transmission,　thereby　significantly　impacting　the　performance　and　reliability　of　the　circuit.　Thus,　to　further　improve　the　routability　of　the　circuit,　it　is　also　critical　to　realize　an　accurate　estimation　of　the　timing　delay　within　the　track　assignment　stage.　Existing　heuristic　track　assignment　algorithms,　however,　are　prone　to　local　optimality,　and　thus　fail　to　provide　accurate　routability　estimations.　In　this　article,　we　propose　an　enhanced　scalable　parallel　track　assignment　algorithm　called　SPTA　2.0　for　VLSI　design,　employing　a　two-stage　partition　strategy　and　considering　timing　delay.　First,　the　proposed　algorithm　achieves　efficient　assignment　of　all　wires　by　considering　the　routing　information　from　both　the　global　and　local　nets.　Second,　the　overlap　cost,　the　blockage　cost,　and　the　wirelength　cost　can　be　minimized　to　significantly　improve　the　routability.　Third,　a　critical　wire　controlling　strategy　is　proposed　to　optimize　signal　timing　delays　inside　nets.　Finally,　a　two-stage　partition　strategy　and　a　panel-subpanel-level　parallelism　are　designed　to　further　reduce　the　runtime,　improving　the　scalability　of　the　proposed　methodology.　Experimental　results　on　multiple　benchmarks　demonstrate　that　the　proposed　method　provides　better　routability　estimations,　and　leads　to　superior　track　assignment　solutions　compared　with　existing　algorithms.　©　2025　Copyright　held　by　the　owner/author(s).　Publication　rights　licensed　to　ACM.