Circuit　partitioning　plays　a　crucial　role　in　very　large-scale　integrated　circuit　(VLSI)　physical　design　automation.　With　current　trends,　partitioning　with　multiple　objectives　which　includes　cutsize,　area,　delay,　and　power　obtains　much　concentration.　In　this　paper,　a　multi-objective　greedy　randomized　adaptive　search　procedure　(GRASP)　is　presented　for　simultaneous　cutsize　and　circuit　delay　minimization.　Each　objective　is　assigned　a　preference　or　weight　to　direct　the　search　procedure　and　generate　a　variety　of　efficient　solutions　by　changing　the　preference.　To　get　a　good　initial　partition　with　minimal　cutsize　and　circuit　delay,　the　gain　of　each　module　in　a　circuit　is　computed　by　considering　both　signal　nets　and　circuit　delay.　The　performance　of　the　proposed　algorithm　is　evaluated　on　a　standard　set　of　partitioning　benchmark.　The　experimental　results　show　that　the　proposed　algorithm　can　generate　a　set　of　Pareto　optimal　solutions　and　is　efficient　for　tackling　multi-objective　circuit　partitioning.　Copyright　©　2012　Editorial　Department　of　Journal　of　Donghua　University.