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author:

Wu, H. (Wu, H..) [1] | Dong, W. (Dong, W..) [2] | Tang, L. (Tang, L..) [3]

Indexed by:

Scopus

Abstract:

In this paper., the topology of DC circuit breaker is proposed., when the fault current occurs., the sampling circuit detects that the current exceeds the threshold., and immediately starts the driving power supply to quickly shut down the JFET., but the JFET is susceptible to the influence of line parasitic inductance in the process of fault current removal., and then there is a serious overvoltage problem., the overvoltage suppression circuit is proposed., its working principle is analyzed in detail and the circuit parameters are designed., and finally., the circuit breaker prototype is developed and experimentally verified. The results show that the circuit breaker has good rapidity and overvoltage suppression effect. © 2024 IEEE.

Keyword:

buffer circuit DC circuit breaker JFET overvoltage parasitic inductance

Community:

  • [ 1 ] [Wu H.]School of Electrical Engineering and Automation, Fuzhou University, Fuzhou, China
  • [ 2 ] [Dong W.]Silk Processing Workshop, Xiamen Tobacco Industry Co. Ltd, Xiamen, China
  • [ 3 ] [Tang L.]School of Electrical Engineering and Automation, Fuzhou University, Fuzhou, China

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Source :

ISSN: 2161-7481

Year: 2024

Page: 1359-1363

Language: English

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 3

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