Clock　tree　synthesis　(CTS)　constructs　an　efficient　clock　tree,　meeting　design　constraints　and　minimizing　resource　usage.　It　serves　as　a　bridge　between　placement　and　routing,　facilitating　concurrent　optimization　of　multiple　design　objectives.　To　construct　a　clock　tree　with　lower　latency　and　load　capacitance　while　maintaining　a　specified　skew　constraint,　we　introduce　skew-latency-load　tree　(SLLT)　which　combines　the　merits　of　bound　skew　tree　and　Steiner　shallow-light　tree,　along　with　an　analysis　and　demonstration　of　the　boundaries　of　these　two　tree　types.　We　propose　a　method　for　constructing　SLLT,　which　significantly　reduces　both　the　maximum　latency　and　load　capacitance　compared　to　previous　methods　while　ensuring　skew　control.　Combining　this　routing　topology　generation　method,　we　introduce　a　hierarchical　CTS　framework,　and　it　is　constructed　by　integrating　partition　schemes　and　buffering　optimization　techniques.　We　validate　our　solution　at　28nm　process　technology,　demonstrating　superior　performance　compared　to　the　solutions　of　OpenROAD　and　advanced　commercial　tool.　Our　approach　outperforms　in　all　metrics　(max　latency,　skew,　buffer　number,　clock　capacitance),　achieving　a　significant　reduction　in　latency　of　29.45%　compared　to　OpenROAD　and　6.75%　compared　to　the　commercial　tool.　©　2024　Copyright　is　held　by　the　owner/author(s).　Publication　rights　licensed　to　ACM.