Detailed　routing　has　become　more　challenging　in　modern　circuit　designs　due　to　the　extreme　scaling　of　chip　size　and　the　additional　complicated　design　rules.　In　this　paper,　we　present　an　effective　detailed　routing　algorithm　for　advanced　technology　nodes　with　the　aim　to　optimize　the　total　routing　wirelength.　Under　the　constraints　of　blockages　and　pin　information,　we　first　present　a　shape-based　connection　candidates　generation　to　generate　crucial　connection　points,　which　significantly　reduces　searching　connection　points　for　the　following　detailed　routing　process.　Then,　a　valid　net＇s　connection　edges　selection　strategy　is　presented　to　choose　routing　direction　edges,　and　a　fast　scanning　line　technique　is　applied　to　remove　invalidate　edges.　Finally,　considering　the　complex　design　rules　in　the　advanced　technology　nodes,　we　introduce　a　Steiner　minimal　tree　based　algorithm　to　obtain　an　initial　detailed　routing　result,　and　further　propose　a　complexity-driven　post-processing　and　refinement　stage　to　strike　out　redundant　points　and　merge　adjacent　edges.　Experimental　results　on　industry　benchmarks　show　that,　comparing　with　classical　algorithms,　our　proposed　algorithm　not　only　achieves　100%　routability　on　real　industrial　cases　but　also　obtains　shorter　total　wirelength.　©　2019　IEEE.