Sparse　matrix　multiplication　(SpMM)　plays　a　critical　role　in　high-performance　computing　applications,　such　as　deep　learning,　image　processing,　and　physical　simulation.　Field-Programmable　Gate　Arrays　(FPGAs),　with　their　configurable　hardware　resources,　can　be　tailored　to　accelerate　SpMMs.　There　has　been　considerable　research　on　deploying　sparse　matrix　multipliers　across　various　FPGA　platforms.　However,　the　FPGA-based　design　of　sparse　matrix　multipliers　still　presents　numerous　challenges.　Therefore,　it　is　necessary　to　summarize　and　organize　the　current　work　to　provide　a　reference　for　further　research.　This　article　first　introduces　the　computational　method　of　SpMM　and　categorizes　the　different　challenges　of　FPGA　deployment.　Following　this,　we　introduce　and　analyze　a　variety　of　state-of-the-art　FPGA-based　accelerators　tailored　for　SpMMs.　In　addition,　a　comparative　analysis　of　these　accelerators　is　performed,　examining　metrics　including　compression　rate,　throughput,　and　resource　utilization.　Finally,　we　propose　potential　research　directions　and　challenges　for　further　study　of　FPGA-based　SpMM　accelerators.