Graph　convolutional　networks　(GCNs)　based　on　convolutional　operations　have　been　developed　recently　to　extract　high-level　representations　from　graph　data.　They　have　shown　advantages　in　many　critical　applications,　such　as　recommendation　system,　natural　language　processing,　and　prediction　of　chemical　reactivity.　The　problem　for　the　GCN　is　that　its　target　applications　generally　pose　stringent　constraints　on　latency　and　energy　efficiency.　Several　studies　have　demonstrated　that　field　programmable　gate　array　(FPGA)-based　GCNs　accelerators,　which　balance　high　performance　and　low　power　consumption,　can　continue　to　achieve　orders-of-magnitude　improvements　in　the　inference　of　GCNs　models.　However,　there　still　are　many　challenges　in　customizing　FPGA-based　accelerators　for　GCNs.　It　is　necessary　to　sort　out　the　current　solutions　to　these　challenges　for　further　research.　For　this　purpose,　we　first　summarize　the　four　challenges　in　FPGA-based　GCNs　accelerators.　Then　we　introduce　the　process　of　the　typical　GNN　algorithm　and　several　examples　of　representative　GCNs.　Next,　we　review　the　FPGA-based　GCNs　accelerators　in　recent　years　and　introduce　their　design　details　according　to　different　challenges.　Moreover,　we　compare　the　key　metrics　of　these　accelerators,　including　resource　utilization,　performance,　and　power　consumption.　Finally,　we　anticipate　the　future　challenges　and　directions　for　FPGA-based　GCNs　accelerators:　algorithm　and　hardware　co-design,　efficient　task　scheduling,　higher　generality,　and　faster　development.