A　transient　response　improved　digital　low　dropout　regulator(D-LDO)　is　proposed　in　this　work.　With　an　proposed　approximate　constant　and　exponential-adaptive　gain　(CEAG)　analog-to-frequency　domain　converter　(AFC),　the　DLDO　achieves　improved　overshoot　(or　undershoot)　voltages　with　optimized　settling　time.　In　the　steady　state,　D-LDO　acts　as　a　conventional　D-LDO　because　of　approximate　constant　open　loop　gain.　While　in　the　fine　and　coarse　regulation　state,　DLDO　equivalent　open　loop　gain　transfers　to　approximate　exponential-adaptive　one　to　improve　the　settling　time.　Simultaneously,　steady　state　power　needs　not　to　be　traded-off.　Fabricated　with　180nm　standard　CMOS　process,　the　measurement　results　show　that　undershoot　and　overshoot　voltages　are　45mV　and　25mV　with　load　steps　of　2　to　90mA　(overshoot　otherwise)　and　an　edge　time　40ns,　respectively.　The　settling　time　and　quiescent　power　achieve　about　350ns　and　63　mu　W,　respectively.