The　expansion　of　the　IC　dimension　is　ushering　in　a　more-than-Moore　era,　necessitating　corresponding　EDA　tools.　Existing　TSV-based　3D　placers　focus　on　minimizing　cuts,　while　burgeoning　F2F-bonded　ICs　features　dense　interconnection　between　two　planar　die.　Towards　this　novel　structure,　we　proposed　an　integrated　adaptation　methodology　upon　mature　one-die-based　placement　strategies.　First,　we　instructively　utilized　a　one-die　placer　to　provide　a　statistical　looking-ahead　net　diagnosis.　The　netlist　henceforth　shall　be　coarsened　topologically　and　geometrically　with　a　multi-level　framework.　Level　by　level,　the　partition　will　be　refined　according　to　a　multi-objective　gain　formulation,　including　cut　expectation,　heterogeneous　row　height,　and　balanced　cell　distribution.　Given　the　partition,　we　synchronized　the　behavior　of　analytical　planar　placers　by　balancing　the　density　and　wirelength　objective　function　among　asymmetric　layers.　Finally,　the　result　will　be　further　improved　by　heuristic　bonding　terminals＇　detail　placement　and　a　post-place　partition　adjustment.　Compared　to　the　top　three　winners　of　the　2022　CAD　Contest　at　ICCAD,　experiment　results　show　that　our　fine-grained　fusion　upon　partitioning　and　placement　gets　the　best　normalized　average　wirelength　with　a　fairly　reasonable　runtime　under　all　3D　architectural　constraints.　©　2024　IEEE.