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author:

Lan, Tingshen (Lan, Tingshen.) [1] | Li, Xingquan (Li, Xingquan.) [2] | Chen, Jianli (Chen, Jianli.) [3] | Yu, Jun (Yu, Jun.) [4] | He, Lei (He, Lei.) [5] | Dong, Senhua (Dong, Senhua.) [6] | Zhu, Wenxing (Zhu, Wenxing.) [7] (Scholars:朱文兴) | Chang, Yao-Wen (Chang, Yao-Wen.) [8]

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EI Scopus

Abstract:

Metal fill insertion has become an essential step to reduce dielectric thickness variation and improve pattern uniformity, which is important in mitigating process variations, thereby achieving better manufacturing yield. However, metal fills could induce coupling capacitance, which is not often considered in existing works that typically focus more on pattern density uniformity, incurring significant problems in timing closure. In this paper, we address the timing-aware fill insertion problem that considers the total capacitance and density constraints simultaneously. First, initial metal fill insertion and design-rule-aware legalization are used to quickly obtain an initial fill insertion solution. Second, from critical conductors to powers/grounds in a circuit, we divide conductors into different equivalent paths and then construct a capacitance graph to globally reduce the capacitance of each equivalent path. Third, we present a density-aware coupling capacitance optimization method and a fast Monte Carlo based fill selection to further reduce the coupling capacitance between any pair of conductors. Finally, we present a density-aware fill deletion method to reduce the fill amounts. We evaluate the performance of our algorithm based on the benchmarks of the 2018 CAD Contest at ICCAD and its official contest evaluator. Compared with the first place team of the contest and the state-of-the-art work, experimental results show that our algorithm achieves the lowest total capacitance and the least fill amount for each benchmark. © 2019 IEEE.

Keyword:

Benchmarking Capacitance Computer aided design Monte Carlo methods Timing circuits

Community:

  • [ 1 ] [Lan, Tingshen]Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, China
  • [ 2 ] [Li, Xingquan]Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, China
  • [ 3 ] [Chen, Jianli]Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, China
  • [ 4 ] [Chen, Jianli]State Key Lab of ASIC and System, Fudan University, China
  • [ 5 ] [Yu, Jun]State Key Lab of ASIC and System, Fudan University, China
  • [ 6 ] [He, Lei]Department of Electrical Engineering, University of California at Los Angeles, United States
  • [ 7 ] [Dong, Senhua]Empyrean Software, Inc, Beijing; 10000, China
  • [ 8 ] [Zhu, Wenxing]Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, China
  • [ 9 ] [Chang, Yao-Wen]Graduate Institute of Electronics Engineering, National Taiwan University, Taipei; 10617, Taiwan
  • [ 10 ] [Chang, Yao-Wen]Department of Electrical Engineering, National Taiwan University, Taipei; 10617, Taiwan

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ISSN: 1092-3152

Year: 2019

Volume: 2019-November

Language: English

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count: 3

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 0

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