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author:

Pan, Y. (Pan, Y..) [1] | Liu, G. (Liu, G..) [2] (Scholars:刘耿耿) | Huang, X. (Huang, X..) [3] | Li, Z. (Li, Z..) [4] | Huang, H. (Huang, H..) [5] | Liang, C. (Liang, C..) [6] | Wang, Q. (Wang, Q..) [7] | Kim, C. (Kim, C..) [8] | Ho, T. (Ho, T..) [9]

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Scopus

Abstract:

With the advances in microfluidics, electrowettingon-dielectric (EWOD) chips have widely been applied to various biological and chemical laboratory protocols. Glass-based EWOD chips with non-regular electrodes are proposed, which allow more reliable droplet operations and facilitate the integration of optical sensors for many biochemical applications. Furthermore, non-regular electrode designs are utilized in EWOD chips, e.g., interdigitated electrodes for more reliable droplet manipulation, custom shaped electrodes for specific applications like concentric heating, etc. However, due to the technical challenges of fabricating multi-layer interconnection on the glass substrate, e.g., unreliable process and high cost, both control electrodes and wires are fabricated with a single-layer configuration, which poses significant challenges to pin selection for non-regular electrodes. In this paper, we propose a minimum-cost flow-based routing algorithm called NR-Router+ that features efficient and robust routing for single-layer EWOD chips with non-regular electrodes. To the best of our knowledge, this is the first work that overcomes the aforementioned challenges. We construct a minimum-cost flow algorithm to generate optimal routing paths followed by a light-weight model to handle flow capacity. A grid reduction strategy is proposed to reduce the computational overhead. Additionally, a flow collocation algorithm based on integer linear programming is presented to efficiently prevent wire overlapping. Experimental results show that NR-Router+ achieves 100% routability while minimizing wirelength with shorter run time. Moreover, NR-Router+ can generate mask files feasible for manufacturing via adjustments of design parameters, thus demonstrating its robustness and efficiency. IEEE

Keyword:

Costs Electrodes Pins Routing Shape Substrates Wires

Community:

  • [ 1 ] [Pan Y.]School of Computer Science, Northwestern Polytechnical University, Xi’an, China
  • [ 2 ] [Liu G.]College of Computer and Data Science, Fuzhou University, Fuzhou, China
  • [ 3 ] [Huang X.]School of Computer Science, Northwestern Polytechnical University, Xi’an, China
  • [ 4 ] [Li Z.]Silicon Engineering Group, Apple Inc, Cupertino, CA, USA
  • [ 5 ] [Huang H.]Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan
  • [ 6 ] [Liang C.]Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan
  • [ 7 ] [Wang Q.]Mechanical and Aerospace Engineering Department, University of California, LA, USA
  • [ 8 ] [Kim C.]Mechanical and Aerospace Engineering Department, University of California, LA, USA
  • [ 9 ] [Ho T.]Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, Hong Kong

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Source :

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

ISSN: 0278-0070

Year: 2024

Issue: 9

Volume: 43

Page: 1-1

2 . 7 0 0

JCR@2023

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 1

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