Discrete-time　delta-sigma　modulators　(DTDSM)　have　excellent　energy　efficiency　in　low　bandwidth,　high　dynamic　range,　and　high　precision　applications,　making　them　ideal　for　battery-powered　IoT　sensor　devices　with　bandwidths　within　the　kHz　range.　They　achieve　high　signal-to-noise　ratio　(SNR)　and　dynamic　range　(DR)　primarily　through　higher-order　loops,　higher　OSR,　multi-bit　quantizers,　and　multi-stage　noise-shaping　(MASH).　However,　higher-order　loops　can　decrease　the　maximum　stable　amplitude　(MSA),　higher　OSR　increases　system　power　consumption,　multi-bit　quantizers　bring　additional　dynamic　element　matching　(DEM)　overhead,　and　MASH　leads　to　noise　leakage　problems.　Tri-level　quantization　schemes　combine　the　advantages　of　single-bit　and　multi-bit　approaches　[1],　making　them　more　suitable　for　high-energy　efficiency　applications.　SAR　quantizers　have　gained　popularity　in　low-bandwidth　DTDSM　designs　in　recent　years　[2-4].　This　paper　presents　a　third-order　single-loop　DTDSM　based　on　an　asynchronous　1.5-bit　SAR　quantizer,　Tri-level　feedback　CDAC,　and　dynamic　range　enhancement　(DRE)　technique,　eliminating　the　need　for　DEM　overhead.　With　the　assistance　of　DRE　technology,　the　loop　gain　for　small　input　amplitudes　is　enhanced.　This　allows　the　DTDSM　to　achieve　2.3　μW　power　consumption　while　achieving　94.7　dB　DR　and　92.2　dB　SNDR　at　a　700　Hz　bandwidth.　As　a　result,　the　Schreier　FoM　for　SNDR　and　DR　is　177　dB　and　179.5　dB,　respectively.　©　2023　IEEE.