With　the　growing　complexity　and　scale　of　FPGA　architectures,　challenges　posed　by　heterogeneity　and　routability　have　become　more　pronounced　in　FPGA　packing.　Conventional　FPGA　packing　algorithms　are　seldom　considered　routability　and　may　lead　to　unroutable　results.　This　paper　addresses　these　challenges　by　proposing　an　effective　routability-driven　packing　algorithm　tailored　for　large-scale　heterogeneous　FPGAs.　The　proposed　algorithm　consists　of　four　major　parts:　(1)　a　LUT-FF　pairing　method　is　presented　to　pack　LUTs　and　FFs　into　LUT-FF　pairs.　(2)　A　novel　BLE　packing　method　is　presented　to　deal　with　the　complex　clock　constraints,　meanwhile　forming　more　HCLB-friendly　BLEs.　(3)　A　congestion-aware　HCLB　packing　technique　is　proposed　to　produce　placement-friendly　netlists　without　degrading　routability.　(4)　An　effective　and　accurate　routing　congestion　estimation　method　is　proposed　to　guide　the　packing　process.　Based　on　the　ISPD　2017　clock-aware　FPGA　placement　contest　benchmarks,　experimental　results　show　that　our　algorithm　outperforms　three　state-of-the-art　FPGA　placers　by　9.8%,　8.2%,　and　3.4%　on　routed　wirelength,　respectively.　©　2023