Modern　FPGAs　often　contain　heterogeneous　architectures　and　clocking　resources　which　must　be　considered　to　achieve　desired　solutions.　As　the　design　complexity　keeps　growing,　placement　has　become　critical　for　FPGA　timing　closure.　In　this　paper,　we　present　an　analytical　placement　algorithm　for　heterogeneous　FPGAs　to　optimize　its　worst　slack　and　clock　constraints　simultaneously.　First,　a　heterogeneity-aware　and　memory-friendly　delay　model　is　developed　to　accurately　and　rapidly　assess　each　connection　delay.　Then,　a　two-stage　clock　region　refinement　method　is　presented　to　effectively　resolve　the　clock　and　resource　violations.　Finally,　we　develop　a　novel　timing-based　co-optimization　method　to　generate　optimized　placement　without　any　clocking　violations.　Compared　with　the　state-of-the-art　placer　based　on　the　advanced　commercial　tool　Xilinx　Vivado　2019.1　with　the　Xilinx　7　Series　FPGA　architecture,　our　algorithm　achieves　the　best　worst　slack　and　routed　wirelength　while　satisfying　all　clock　constraints.　©　2021　EDAA.