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author:

Liu, Geng-Geng (Liu, Geng-Geng.) [1] | Bao, Chen-Peng (Bao, Chen-Peng.) [2] | Wang, Xin (Wang, Xin.) [3] | Guo, Wen-Zhong (Guo, Wen-Zhong.) [4] | Chen, Guo-Long (Chen, Guo-Long.) [5]

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EI PKU CSCD

Abstract:

As a key step in the physical design of very large scale integration layer assignment plays a very important role in determining the delay of routing solution. At the same timewith the continuous progress of technical nodes the density of the nets is increasing. Interconnect delay is an important factor to evaluate the performance of the routing results. In order to optimize the delay in integrated circuits the existing layer assignment algorithms usually focus on minimizing interconnect delay and via count. Howeverthe existing work either does not consider the assignment of the timing-critical segments in nets or the time critical representation of wire segments is not reasonable which ultimately makes the delay optimization not ideal. For this reason this paper proposes a multi-strategy delay-driven layer assignment for non-default-rule wire techniquewhich mainly includes the following key strategies1In order to avoid the local optimization of the netsa track number aware layer selection strategy is proposed. This strategy enhances the ability of layer assigner to select suitable routing layers for wire segments so that it allows the layer with the largest number of remaining tracks to be given priority in the layer assignment to avoid overflow in the routing layer. 2A multi-index driven initial net sorting strategy is proposed. This strategy fully considers the characteristics of different nets to determine the priority of netsand comprehensively considers multiple indicators such as the wirelengththe number of sink points and the resource of routing tracks to determine the priority of layer assignment for the network so that the high-quality initial layer assignment results is obtained. 3In order to further optimize the delay a wire segment adjusting strategy is proposed. This strategy is adopted to optimize the delay of nets by re-assigning nets and assigning the timing-critical segments on upper layers. 4A wire segment delay optimization strategy is proposed to optimize the delay of nets while eliminating overflow by ripping up and re-assigning the nets which have overflow. This strategy not only makes the final routing result not overflowbut also makes it have better delay. And the proposed algorithm is mainly composed of three stages. First a better initial layer assignment result is obtained through the multi-index driven initial net sorting strategy. Then the proposed algorithm adjusts the routing layer of the timing-critical segments through the wire segment adjusting strategy and then eliminates the overflow while optimizing delay through the wire segment delay optimization strategy. Finally under the condition of satisfying the congestion constraint the proposed algorithm rips up and re-assigns the nets to select a better layer assignment result. In each stage the track number aware layer selection strategy is used in the single net layer assignment so that the track resources of upper layers can be fully utilized. This paper uses the DAC12 benchmarks to verify the effectiveness of the related strategies and the proposed algorithm. The experimental results show that the proposed algorithm can achieve the best performance in both delay and via count among the existing algorithms without overflow. © 2023 Science Press. All rights reserved.

Keyword:

Delay circuits Integrated circuit interconnects Network layers Network routing Timing circuits Wire

Community:

  • [ 1 ] [Liu, Geng-Geng]College of Computer and Data Science, Fuzhou University, Fuzhou; 350116, China
  • [ 2 ] [Liu, Geng-Geng]State Key Laboratory of Computer System and Architecture, Beijing; 100190, China
  • [ 3 ] [Bao, Chen-Peng]College of Computer and Data Science, Fuzhou University, Fuzhou; 350116, China
  • [ 4 ] [Wang, Xin]College of Intelligence and Computing, Tianjin University, Tianjin; 300350, China
  • [ 5 ] [Wang, Xin]Tianjin Key Laboratory of Cognitive Computing and Application, Tianjin; 300350, China
  • [ 6 ] [Guo, Wen-Zhong]College of Computer and Data Science, Fuzhou University, Fuzhou; 350116, China
  • [ 7 ] [Chen, Guo-Long]College of Computer and Data Science, Fuzhou University, Fuzhou; 350116, China

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Source :

计算机学报

ISSN: 0254-4164

Year: 2023

Issue: 4

Volume: 46

Page: 743-760

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count: 1

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 0

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