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author:

Huang, Haishan (Huang, Haishan.) [1] | Chen, Weijie (Chen, Weijie.) [2] | Cai, Zhijie (Cai, Zhijie.) [3] | Huang, Jiarong (Huang, Jiarong.) [4] | Chen, Jianli (Chen, Jianli.) [5]

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EI

Abstract:

In the very large scale integration (VLSI) global routing stage, one of the most critical considerations is how to obtain a proper balance between routing quality and runtime. In this paper, we adopt a multi-threading technique to accelerate various subphases of global routing. To ensure the robustness of routing results, we add a stage called congestion and wire length aware breaking circles algorithm while ensuring to remove the most congested or longest wire segment in the loops. Since routing congestion is the most critical constraint in the global routing phase, we present two accurate cost models to evaluate the routing resources, which can effectively reduce the congestion of routing results. The experiment shows that our proposed method reduces the violations by 28.3% and achieves a 2x faster runtime in benchmarks of the ISPD'19 contest compared with CUGR. © 2022 IEEE.

Keyword:

Computer aided design VLSI circuits

Community:

  • [ 1 ] [Huang, Haishan]Fuzhou University, College of Computer and Data Science, Fuzhou; 350108, China
  • [ 2 ] [Chen, Weijie]Fuzhou University, College of Computer and Data Science, Fuzhou; 350108, China
  • [ 3 ] [Cai, Zhijie]Fudan University, State Key Lab of Asic & System, Shanghai; 200433, China
  • [ 4 ] [Huang, Jiarong]Fuzhou University, College of Computer and Data Science, Fuzhou; 350108, China
  • [ 5 ] [Chen, Jianli]Fudan University, State Key Lab of Asic & System, Shanghai; 200433, China

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Year: 2022

Language: English

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count: 1

ESI Highly Cited Papers on the List: 0 Unfold All

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30 Days PV: 3

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