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author:

Bai, Xiqiong (Bai, Xiqiong.) [1] | Zhu, Ziran (Zhu, Ziran.) [2] | Li, Pingping (Li, Pingping.) [3] | Chen, Jianli (Chen, Jianli.) [4] | Lan, Tingshen (Lan, Tingshen.) [5] | Li, Xingquan (Li, Xingquan.) [6] | Yu, Jun (Yu, Jun.) [7] | Zhu, Wenxing (Zhu, Wenxing.) [8] (Scholars:朱文兴) | Chang, Yao-Wen (Chang, Yao-Wen.) [9]

Indexed by:

EI Scopus SCIE

Abstract:

Metal fill insertion has become an essential step in reducing dielectric thickness variation and improving pattern uniformity, which is important in mitigating process variations, thereby achieving better manufacturing yield. However, metal fills could induce coupling capacitance, which is not often considered in existing works that typically focus more on pattern density uniformity, incurring significant problems in timing closure. However, it is a great challenge to consider three types of capacitances (i.e., area, fringe, and lateral capacitances) with design rules and density constraints at the fill insertion stage simultaneously. This article presents an efficient timing-aware fill insertion algorithm for minimizing the total capacitance and fill amount, considering the density constraints. First, we present an initial metal fill insertion and design-rule-aware legalization to obtain an initial fill insertion solution quickly. Second, from critical conductors to powers/grounds in a circuit, we divide conductors into different equivalent paths and then construct a capacitance graph to reduce the capacitance of each equivalent path globally. Third, we propose a density-aware coupling capacitance optimization method and a fast Monte Carlo-based fill selection to further reduce the coupling capacitance between any pair of conductors. Finally, we present a density-aware fill deletion method to reduce the fill amount. We evaluate the performance of our algorithm on the benchmarks of the 2018 CAD Contest at ICCAD and its official contest evaluator. Compared with the first-place team of the contest and the state-of-the-artwork, experimental results show that our algorithm achieves the lowest total capacitance and the least fill amount in a comparable runtime.

Keyword:

Capacitance Conductors Coupling capacitance Couplings Delays density constraints design rule Dielectrics fill amount Layout Metals timing-aware fill insertion

Community:

  • [ 1 ] [Bai, Xiqiong]Fuzhou Univ, Ctr Discrete Math & Theoret Comp Sci, Fuzhou 350116, Peoples R China
  • [ 2 ] [Li, Pingping]Fuzhou Univ, Ctr Discrete Math & Theoret Comp Sci, Fuzhou 350116, Peoples R China
  • [ 3 ] [Lan, Tingshen]Fuzhou Univ, Ctr Discrete Math & Theoret Comp Sci, Fuzhou 350116, Peoples R China
  • [ 4 ] [Li, Xingquan]Fuzhou Univ, Ctr Discrete Math & Theoret Comp Sci, Fuzhou 350116, Peoples R China
  • [ 5 ] [Zhu, Wenxing]Fuzhou Univ, Ctr Discrete Math & Theoret Comp Sci, Fuzhou 350116, Peoples R China
  • [ 6 ] [Zhu, Ziran]Southeast Univ, Sch Elect Sci & Engn, Natl ASIC Syst Engn Ctr, Nanjing 210096, Peoples R China
  • [ 7 ] [Chen, Jianli]Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
  • [ 8 ] [Yu, Jun]Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
  • [ 9 ] [Chang, Yao-Wen]Natl Taiwan Univ, Grad Inst Elect Engn, Dept Elect Engn, Taipei 106, Taiwan
  • [ 10 ] [Chang, Yao-Wen]Natl Taiwan Univ, Dept Comp Sci & Informat Engn, Taipei 106, Taiwan

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Source :

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

ISSN: 0278-0070

Year: 2022

Issue: 10

Volume: 41

Page: 3529-3542

2 . 9

JCR@2022

2 . 7 0 0

JCR@2023

ESI Discipline: ENGINEERING;

ESI HC Threshold:66

JCR Journal Grade:2

CAS Journal Grade:3

Cited Count:

WoS CC Cited Count: 1

SCOPUS Cited Count: 2

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 1

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