Interconnect　delay　is　a　key　factor　that　affects　the　chip　performance　in　layer　assignment.　Particularly　in　the　advanced　process　technologies　of　5　nm　and　beyond,　interconnect　delay　has　grown　significantly　due　to　the　increase　of　circuit　scale.　Moreover,　coupling　effect　existed　in　wires　reduces　the　accuracy　of　delay　evaluation.　On　the　other　hand,　the　size　of　vias　is　often　ignored　in　layer　assignment,　which　enlarges　the　mismatch　between　global　routing　and　detailed　routing.　To　solve　these　problems,　we　propose　VPT,　a　timing-aware　layer　assignment　algorithm　considering　via　pillars,　which　includes　the　following　five　key　techniques:　1)　via　pillar　structure　combined　with　nondefault-rule　(NDR)　wires　is　adopted　to　form　a　net　delay　optimization　system　for　advanced　process　technologies;　2)　a　synthetical　model　that　can　adapt　to　varying　types　and　sizes　of　both　vias　and　wires　is　designed　to　evaluate　overflow　effectively;　3)　a　sorting　strategy　is　devised　to　reduce　uncertainty　of　layer　assignment　flow　and　improve　stability　of　the　proposed　algorithm;　4)　an　awareness　strategy　based　on　multiaspect　congestion　assessment　is　designed　to　reduce　overflow　significantly;　and　5)　a　net　scalpel　algorithm　is　devised　to　minimize　the　maximum　delay　of　nets,　so　that　the　timing　behaviors　can　be　improved　systematically.　The　experimental　results　on　multiple　benchmarks　confirm　that　the　proposed　algorithm　leads　to　lower　delay　and　less　overflow,　while　achieving　the　best　solution　quality　among　the　existing　algorithms　with　the　shortest　runtime.　©　1982-2012　IEEE.