With　several　divided　stages,　placement　and　routing　are　the　most　critical　and　challenging　steps　in　VLSI　physical　design.　To　ensure　that　physical　implementation　problems　can　be　manageable　and　converged　in　a　reasonable　runtime,　placement/routing　problems　are　usually　further　split　into　several　sub-problems,　which　may　cause　conservative　margin　reservation　and　mis-correlation.　Therefore,　it　is　desirable　to　design　an　algorithm　that　can　accurately　and　efficiently　consider　placement　and　routing　simultaneously.　In　this　paper,　we　propose　a　detailed　placement　and　global　routing　co-optimization　algorithm　while　considering　complex　routing　constraints　to　avoid　conservative　margin　reservation　and　mis-correlation　in　placement/routing　stages.　Firstly,　we　present　a　rapidly　preprocessing　technology　based　on　R-tree　to　improve　the　initial　routing　results.　After　that,　a　BFS-based　approximate　optimal　addressing　algorithm　in　3D　is　designed　to　find　a　proper　destination　for　cell　movement.　We　propose　an　optimal　region　selection　algorithm　based　on　the　partial　routing　solution　to　jump　out　of　the　local　optimal　solution.　Further,　a　fast　partial　net　rip-up　and　rerouted　algorithm　is　used　in　the　process　of　cell　movement.　Finally,　we　adopt　an　efficient　refinement　technique　to　reduce　the　routing　length　further.　Compared　with　the　top　3　winners　according　to　the　2020　ICCAD　CAD　contest　benchmarks,　the　experimental　results　show　that　our　algorithm　achieves　the　best　routing　length　reduction　for　all　cases　with　a　shorter　runtime.　On　average,　our　algorithm　can　improve　0.7%,　1.5%,　and　1.7%　for　the　first,　second,　and　third　place,　respectively.　In　addition,　we　can　still　obtain　the　best　results　after　relaxing　the　maximum　cell　movement　constraint,　which　further　illustrates　the　effectiveness　of　our　algorithm.