This　paper　presents　a　driver　amplifier　with　high　bandwidth-power　efficiency,　high　capacitor-driving　capacity,　and　low　total　harmonic　distortion　(THD).　One　complementary　differential　pair　composed　of　self-cascode　transistors　is　incorporated　to　obtain　a　full　input　voltage　swing.　Flipped　voltage　follower　(FVF)　buffers　are　applied　as　second　stage　to　drive　the　last　class-AB　output　stage.　Moreover,　a　dual-loop　active-feedback　frequency　compensation　(DLAFC)　is　presented,　which　can　stabilize　the　proposed　multistage　amplifier　and　keep　the　dominant　pole　on　high　frequency　to　obtain　high-frequency　total　harmonic　distortion　(THD)　suppression.　To　achieve　a　low-frequency　phase　margin　protection　(PMP),　one　left　half-plane　(LHP)　zero　is　introduced　to　compensate　for　the　nondominant　pole　caused　by　the　load　capacitor.　Meanwhile,　two　high-frequency　LHP　zeros　are　injected　to　achieve　high-frequency　phase　margin　boosting　(PMB)　and　reduce　the　amplifier＇s　settling　time　and　integration　area.　This　proposed　amplifier　is　implemented　in　a　standard　DBH　0.18　mu　m　5　V　CMOS　process,　and　it　achieves　over　115-dB　DC　gain,　150-300　MHz　GBW　under　0-100　p　load　capacitors,　ultra-high　THD2,3　suppression　ranges　from　100　kHz　to　10　MHz　under　1-2　V　output　swing,　and　over　250　V/mu　s　average　slew　rate,　by　only　dissipating　12.5　mW　at　5　V　power　supply.