Floorplanning　is　an　indispensable　step　in　very　large　scale　integration　(VLSI)　design　flow.　Fixed-outline　floorplanning　is　a　challenging　problem　because　it　requires　additional　constraint　that　the　floorplanning　must　meet　both　width　and　height　criteria.　In　this　paper,　a　modified　simulated　annealing　(MSA)　algorithm　is　presented　with　a　new　cost　function　for　this　problem.　In　our　algorithm,　a　two-step　strategy　is　used　to　improve　the　efficiency　of　the　algorithm　and　balance　the　main　function　and　secondary　function.　In　addition,　a　local　search　strategy　is　employed　to　make　sure　a　feasible　solution　can　be　found.　Experimental　results　indicate　that　the　success　rate　of　each　benchmark　is　100%　in　deferent　aspect　ratio.　©　2018　IEEE.