In　this　paper,　two　kinds　of　pipeline　parallel-serial　128-point　Fast　Fourier　Transform　(FFT)　processors　with　mixed-radix　882　and　448　are　investigated.　Pipeline　parallel-serial　processor　has　been　regarded　as　an　optimized　solution　for　FFT.　Based　on　Pipeline　parallel-serial　architecture,　this　paper　proposes　two　kinds　of　implementation　schemes　with　mixed-radix　882　and　448　respectively.　By　comparing　the　area,　power　consumption　and　performance　speed　between　our　Pipeline　parallel-serial　processor　and　other　FFT　implementation,　we　verify　the　performance　characteristics　of　our　schemes.　The　experiment　data　indicate　that　the　mixed-radix　448　scheme　can　reduce　the　system　clock　frequency　by　increasing　area,　and　therefore　save　the　power　consumption.　Meanwhile,　the　mixed-radix　882　scheme　has　an　advantage　in　the　area.　Two　schemes　can　both　finish　the　whole　operation　within　312ns.　So,　they　meet　the　requirements　of　Ultra-Wideband　(UWB)　wireless　communication　systems　for　FFT.　Two　schemes　both　have　regular　data　flow,　then　can　get　the　support　of　pipeline　structures　and　simple　controller　system.　©　2013　ICIC　International.