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学者姓名：施隆照
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Abstract ：
高效视频编码标准(High Efficiency Video Coding,HEVC)作为H.264/AVC的继任者,提高了约2倍的编码效率.但其编码数据的计算复杂度和依赖性的增加,使视频编码器在硬件实现上更加困难.尤其是对编码器视频数据的处理和存取以及编码器内部状态控制的实现带来挑战.本文基于HEVC的宏块编码流程,提出了一种满足整体编码器实时高效运行的视频数据的存取结构和协调编码器各模块的顶层控制的方案.整个设计基于VCS和VIVADO的联合仿真环境验证功能的正确性.并在Xilinx公司的VCU118型号的FPGA上完成上板验证.测试结果表明,综合后的编码器的主频为100 MHz,可以满足编码器实现1080P30@fps的编码需求.
Keyword ：
DDR DDR FPGA FPGA HEVC HEVC 视频编码 视频编码
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| GB/T 7714 | 黄晖 , 施隆照 , 黄霖 . 高效HEVC编码器的硬件架构设计 [J]. | 中国集成电路 , 2025 , 34 (3) : 35-42 . |
| MLA | 黄晖 等. "高效HEVC编码器的硬件架构设计" . | 中国集成电路 34 . 3 (2025) : 35-42 . |
| APA | 黄晖 , 施隆照 , 黄霖 . 高效HEVC编码器的硬件架构设计 . | 中国集成电路 , 2025 , 34 (3) , 35-42 . |
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Abstract ：
本文介绍了基于UVM验证方法学对CPU模块中的ALU运算单元模块的验证平台设计.该验证平台能够对ALU运算单元两级流水系统模块进行完整的功能验证,并且具有可控的复位验证,能够合理控制验证平台的激励输出和覆盖率收集.该验证平台具有良好的复用性和延展性,当CPU模块设计加以补充,更加完善的同时,也可以在验证平台上进行设计的扩充延展,大大提高了验证仿真的效率.
Keyword ：
ALU ALU CPU CPU UVM UVM 验证平台 验证平台
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| GB/T 7714 | 林伟峰 , 施隆照 , 魏陈鸿 et al. ALU模块的UVM验证 [J]. | 中国集成电路 , 2022 , 31 (11) : 30-37 . |
| MLA | 林伟峰 et al. "ALU模块的UVM验证" . | 中国集成电路 31 . 11 (2022) : 30-37 . |
| APA | 林伟峰 , 施隆照 , 魏陈鸿 , 马颖颖 . ALU模块的UVM验证 . | 中国集成电路 , 2022 , 31 (11) , 30-37 . |
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Abstract ：
本文采用"知识传授与价值引领相结合",将思政元素融入《数字集成电路设计》课程教学目标,提出结合课程内容选取思政内容切入点,建立课程思政资料库,持续优化课程思政内容,在潜移默化中坚定学生理想信念,促使本专业学生真正成长为心系社会并有时代担当的集成电路设计人才,推动我国集成电路向更高水平迈进.
Keyword ：
思政资料库 思政资料库 教学目标 教学目标 数字集成电路设计 数字集成电路设计 课程思政 课程思政
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| GB/T 7714 | 王仁平 , 施隆照 , 江浩 . 将思政元素融入《数字集成电路设计》教学目标和课程内容 [J]. | 科教导刊-电子版（下旬） , 2022 , (2) : 159-160 . |
| MLA | 王仁平 et al. "将思政元素融入《数字集成电路设计》教学目标和课程内容" . | 科教导刊-电子版（下旬） 2 (2022) : 159-160 . |
| APA | 王仁平 , 施隆照 , 江浩 . 将思政元素融入《数字集成电路设计》教学目标和课程内容 . | 科教导刊-电子版（下旬） , 2022 , (2) , 159-160 . |
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Thanks to its flexible coding structure, high-efficiency video coding (HEVC) can save more coding bit rates than the previous standard, H.264. However, it also increases the complexity of integer-pixel motion estimation (IME). To speed up the encoding process, we propose a parallel spiral search (PSS) algorithm, which features the following characteristics and advantages. First, the proposed algorithm is hardware-friendly. PSS has both a fix search order that cuts the correlation between search points and a high data reuse level that facilitates the pipeline application in hardware implementation. Second, the PSS algorithm processes all prediction units (PU) blocks in parallel, which speeds up the RD calculation. Finally, the early termination strategy is proposed to end the search for unnecessary search points and further reduce search time. Experimental results show that the proposed algorithm outperforms other popular hardware-oriented IME algorithms in terms of coding speed, with the same loss of RD performance. Compared with the default full search algorithm (FSA) in the HEVC test model HM-16.7, the proposed algorithm achieves average time saving ratio of up to 92.55%, with BD-PSNR loss of 0.056 dB and an increase by 1.38% in terms of BD-BR.
Keyword ：
Hardware-friendly motion estimation Hardware-friendly motion estimation HEVC HEVC Inter prediction Inter prediction Parallel spiral search Parallel spiral search
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| GB/T 7714 | Shi, Long-Zhao , Zhang, Zhiyong , Luo, Long et al. Parallel spiral search algorithm applied to integer motion estimation [J]. | SIGNAL PROCESSING-IMAGE COMMUNICATION , 2021 , 95 . |
| MLA | Shi, Long-Zhao et al. "Parallel spiral search algorithm applied to integer motion estimation" . | SIGNAL PROCESSING-IMAGE COMMUNICATION 95 (2021) . |
| APA | Shi, Long-Zhao , Zhang, Zhiyong , Luo, Long , Yang, Xiuzhi , Chen, Zhifeng , Yang, Xiaoling et al. Parallel spiral search algorithm applied to integer motion estimation . | SIGNAL PROCESSING-IMAGE COMMUNICATION , 2021 , 95 . |
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离散余弦变换(Discrete Cosine Transform,DCT)是新一代视频编码标准(High Efficiency Video Coding,HEVC)中的重要模块之一,有着去除空间冗余,有效压缩图像信息的功能.为了适应多尺寸变换与适应超清视频信号实时编码处理的问题,提出一种基于FPGA的高速变换架构,它能高效处理各种变换尺寸的DCT运算过程,各尺寸变换都通过蝶形算法与利用移位求和代替常规乘法器实现,以降低逻辑资源的消耗.综合结果显示,与现有算法相比,本文架构在计算速度、吞吐率和资源消耗上有较大优势.在Altera的Stratix IV器件下综合工作频率为217 MHz,可支持30帧/秒4096×2160分辨率的超高清视频信号的实时处理.
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| GB/T 7714 | 宋佳柔 , 施隆照 . 一种 HEVC 高速并行的DCT 架构 [J]. | 中国集成电路 , 2021 , 30 (11) : 50-55 . |
| MLA | 宋佳柔 et al. "一种 HEVC 高速并行的DCT 架构" . | 中国集成电路 30 . 11 (2021) : 50-55 . |
| APA | 宋佳柔 , 施隆照 . 一种 HEVC 高速并行的DCT 架构 . | 中国集成电路 , 2021 , 30 (11) , 50-55 . |
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Abstract ：
High efficiency video coding is the most widely used video coding standard. It has higher coding performance compared with its predecessor, H.264, but it also has higher computational complexity. Interprediction is the most computationally intensive part of the entire video encoding process. Selecting the optimal interprediction mode by the rate-distortion cost calculation function requires substantial complex calculation and memory access, thus greatly increasing the difficulty of real-time hardware encoding. This study proposes to replace the traditional complex error square sum calculation with an estimation method for distortion and rate. The estimation of distortion uses the Hadamard-transformed sum of absolute transformation difference instead of the complex calculation of the sum of squared difference, whereas the estimation of rate is obtained by weighting the number of prediction units (PUs). The experiment proves that the proposed interprediction rate-distortion cost calculation model can greatly reduce computational complexity when BD-rate is increased by 3.02%. In hardware implementation, the value of rate can be obtained by indexing the number of PUs, and the resource expenditure is small.
Keyword ：
Hardware architecture Hardware architecture High efficiency video coding (HEVC) High efficiency video coding (HEVC) Interprediction Interprediction Rate-distortion optimisation (RDO) Rate-distortion optimisation (RDO)
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| GB/T 7714 | Shi, Long-zhao , Yan, Danyu , Hong, Xiaojian et al. Algorithm optimisation and hardware implementation of interprediction mode decision [J]. | JOURNAL OF REAL-TIME IMAGE PROCESSING , 2020 . |
| MLA | Shi, Long-zhao et al. "Algorithm optimisation and hardware implementation of interprediction mode decision" . | JOURNAL OF REAL-TIME IMAGE PROCESSING (2020) . |
| APA | Shi, Long-zhao , Yan, Danyu , Hong, Xiaojian , Huang, Bo , Yang, Xiuzhi . Algorithm optimisation and hardware implementation of interprediction mode decision . | JOURNAL OF REAL-TIME IMAGE PROCESSING , 2020 . |
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Merge mode is a new tool for improving inter-frame coding efficiency in high-efficiency video coding. This tool can save the bitrate for the motion vector by sharing this vector with neighboring blocks. Merge is a process that selects a candidate motion vector by calculating the cost of rate-distortion. However, this process requires a large number of complex computations and memory access, thereby resulting in the low efficiency of hardware implementation. This paper proposes a new Merge candidate decision scheme that determines the most favorable Merge candidate from a full list of candidates by comparing the sum of absolute transformed difference with the weighted header bit instead of performing a complex calculation for sum of squared difference and entropy coding process in HM16.7. The simulation results show that the performance of the proposed algorithm is close to that of HM16.7 and increases the BD-rate only by 0.22-1.21%. The multilevel pipelines architecture is also exploited in the hardware design. The weighted header bit operation is performed by using the look-up table, which reduces both the complexity and encoding clock cycle. The designed system is implemented with a register transfer level code. The synthesis results from the Design Compiler show that compared with other architecture, the proposed architecture offers great advantages in resource utilization and can process 1920 x 1080 at 353 frame/s for P-slices with a clock frequency of 1057 MHz and logic gate count of 285.2 K.
Keyword ：
Hardware architecture Hardware architecture High-efficiency video coding (HEVC) High-efficiency video coding (HEVC) Merge mode Merge mode Rate-distortion optimization (RDO) Rate-distortion optimization (RDO) Sum of absolute transformed difference (SATD) Sum of absolute transformed difference (SATD)
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| GB/T 7714 | Shi, Long-zhao , Gao, Xiaohong , Yang, Xiuzhi et al. Algorithm optimization and hardware implementation for Merge mode in HEVC [J]. | JOURNAL OF REAL-TIME IMAGE PROCESSING , 2020 , 17 (3) : 623-630 . |
| MLA | Shi, Long-zhao et al. "Algorithm optimization and hardware implementation for Merge mode in HEVC" . | JOURNAL OF REAL-TIME IMAGE PROCESSING 17 . 3 (2020) : 623-630 . |
| APA | Shi, Long-zhao , Gao, Xiaohong , Yang, Xiuzhi , Chen, Zhifeng , Zheng, Mingkui . Algorithm optimization and hardware implementation for Merge mode in HEVC . | JOURNAL OF REAL-TIME IMAGE PROCESSING , 2020 , 17 (3) , 623-630 . |
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本设计是一种以基于上下文的自适应二进制算术编码(CABAC)为熵编码的高效视频编码方案,通过(CABAC)硬件结构的输入输出模块优化和算术编码模块优化来提高整体架构的效率及主频.在输入模块优化方面,采用四级缓存输入和残差系数优化传输;在算术编码模块优化方面,通过上下文模型索引预读取、预归一化查表和并入串出码流输出设计,提高整体架构的工作效率及主频,降低资源消耗,实现高效流水线高主频硬件架构.硬件设计使用90 nm标准单元库进行综合,可在工作频率为370 MHz下实现流水线,使用电路门数为43.49×103.该处理速率及吞吐率可支持HEVC标准的通用测试条件下1080 P视频30帧·s-1的实时编码.
Keyword ：
CABAC CABAC 吞吐率 吞吐率 熵编码 熵编码 硬件设计 硬件设计 高效视频编码 高效视频编码
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| GB/T 7714 | 傅晨 , 郑明魁 , 陈志峰 et al. 一种高效的CABAC熵编码硬件设计 [J]. | 福州大学学报（自然科学版） , 2020 , 48 (2) : 174-180 . |
| MLA | 傅晨 et al. "一种高效的CABAC熵编码硬件设计" . | 福州大学学报（自然科学版） 48 . 2 (2020) : 174-180 . |
| APA | 傅晨 , 郑明魁 , 陈志峰 , 施隆照 , 王炎 . 一种高效的CABAC熵编码硬件设计 . | 福州大学学报（自然科学版） , 2020 , 48 (2) , 174-180 . |
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提出一种基于Wallace树优化的HEVC/H.265分像素插值滤波算法的实现方案.模块采用按行流水插值架构,通过Wallace树压缩器对插值过程中的各项进行压缩,仅在最终输出结果时使用加法器.该算法不仅减少了硬件面积,而且提高了模块可工作的最高频率.将所提算法在硬件上进行验证,硬件设计以Verilog HDL语言描述,以8 px×8 px大小PU为最小插值单元,使用Modelsim进行功能仿真验证,在Synopsys Design Com-piler中以SAED(Synopsys Armenia education department)32 nm标准单元库进行综合,模块可达到的最高工作频率为636.9 MHz,逻辑门数为32960,吞吐率为11.3 px/时钟周期.
Keyword ：
HEVC HEVC Wallace树 Wallace树 分像素插值 分像素插值 视频编码 视频编码
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| GB/T 7714 | 罗隆 , 施隆照 , 洪晓剑 et al. 采用Wallace树优化的分像素运动估计插值滤波算法 [J]. | 福州大学学报（自然科学版） , 2020 , 48 (2) : 181-186 . |
| MLA | 罗隆 et al. "采用Wallace树优化的分像素运动估计插值滤波算法" . | 福州大学学报（自然科学版） 48 . 2 (2020) : 181-186 . |
| APA | 罗隆 , 施隆照 , 洪晓剑 , 严丹钰 . 采用Wallace树优化的分像素运动估计插值滤波算法 . | 福州大学学报（自然科学版） , 2020 , 48 (2) , 181-186 . |
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Abstract ：
新一代视频编码标准(High Efficiency Video Coding,HEVC)与AVC/H.264相比,在相同视觉质量条件下可以节省50％的码率,但其计算的复杂度以及数据的依赖性,给实现实时编码带来巨大的挑战.本文从硬件实现的角度针对CTU块的编码流程,提出一种高效并行流水处理方案,将整个编码过程划分成相互独立的率失真优化(RDO)、重构和熵编码三个阶段,实现整个编码过程流水作业.并设计实现了编码器各模块之间的数据高效交换存储架构,确保流水线不断流或少断流,提高了整个编码器的运行效率.
Keyword ：
AVC/H.264 AVC/H.264 HEVC HEVC 流水线 流水线 硬件实现 硬件实现
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| GB/T 7714 | 王炎 , 施隆照 , 李忠旺 et al. HEVC的高效并行流水编码器设计 [J]. | 广播电视网络 , 2020 , 27 (1) : 93-97 . |
| MLA | 王炎 et al. "HEVC的高效并行流水编码器设计" . | 广播电视网络 27 . 1 (2020) : 93-97 . |
| APA | 王炎 , 施隆照 , 李忠旺 , 傅晨 . HEVC的高效并行流水编码器设计 . | 广播电视网络 , 2020 , 27 (1) , 93-97 . |
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