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author:

Dong, Chen (Dong, Chen.) [1] | He, Guorong (He, Guorong.) [2] | Liu, Ximeng (Liu, Ximeng.) [3] | Yang, Yang (Yang, Yang.) [4] | Guo, Wenzhong (Guo, Wenzhong.) [5]

Indexed by:

EI

Abstract:

Since integrated circuits are performed by several untrusted manufacturers, malicious circuits (hardware Trojans) can be implanted in any stage of the Internet-of-Things (IoT) devices. With the globalization of the IoT device manufacturing technologies, protecting the system-on-chip (SoC) security is always the keys issue for scientists and IC manufacturers. The existing SoC high-level synthesis approaches cannot guarantee both register-transfer-level and gate-level security, such as some formal verification and circuit characteristic analysis technologies. Based on the structural characteristics of hardware Trojans, we propose a multi-layer hardware Trojan protection framework for the Internet-of-Things perception layer called RG-Secure, which combines the third-party intellectual property trusted design strategy with the scan-chain netlist feature analysis technology. Especially at the gate level of chip design, our RG-Secure is equipped with a distributed, lightweight gradient lifting algorithm called lightGBM. The algorithm can quickly process high-dimensional circuit feature information and effectively improve the detection efficiency of hardware Trojans. In the meanwhile, a common evaluation index F-measure is used to prove the effectiveness of our method. The experiments show that RG-Secure framework can simultaneously detect register-transfer-level and gate-level hardware Trojans. For the trust-HUB benchmarks, the optimized lightGBM classifier achieves up to 100% true positive rate and 94% true negative rate; furthermore, it achieves 99.8% average F-measure and 99% accuracy, which shows a promising approach to ensure security during the design stage. © 2013 IEEE.

Keyword:

Electric network analysis Hardware security High level synthesis Integrated circuit design Internet of things Malware Manufacture Programmable logic controllers System-on-chip Trusted computing

Community:

  • [ 1 ] [Dong, Chen]College of Mathematics and Computer Science, Fuzhou University, Fuzhou; 350116, China
  • [ 2 ] [Dong, Chen]Key Laboratory of Information Security of Network Systems, Fuzhou University, Fuzhou; 350116, China
  • [ 3 ] [He, Guorong]College of Mathematics and Computer Science, Fuzhou University, Fuzhou; 350116, China
  • [ 4 ] [He, Guorong]Key Laboratory of Information Security of Network Systems, Fuzhou University, Fuzhou; 350116, China
  • [ 5 ] [Liu, Ximeng]College of Mathematics and Computer Science, Fuzhou University, Fuzhou; 350116, China
  • [ 6 ] [Liu, Ximeng]Key Laboratory of Information Security of Network Systems, Fuzhou University, Fuzhou; 350116, China
  • [ 7 ] [Yang, Yang]College of Mathematics and Computer Science, Fuzhou University, Fuzhou; 350116, China
  • [ 8 ] [Yang, Yang]Key Laboratory of Information Security of Network Systems, Fuzhou University, Fuzhou; 350116, China
  • [ 9 ] [Guo, Wenzhong]College of Mathematics and Computer Science, Fuzhou University, Fuzhou; 350116, China
  • [ 10 ] [Guo, Wenzhong]Fujian Provincial Key Laboratory of Network Computing and Intelligent Information Processing, Fuzhou University, Fuzhou; 350116, China

Reprint 's Address:

  • [guo, wenzhong]fujian provincial key laboratory of network computing and intelligent information processing, fuzhou university, fuzhou; 350116, china;;[guo, wenzhong]college of mathematics and computer science, fuzhou university, fuzhou; 350116, china

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Source :

IEEE Access

Year: 2019

Volume: 7

Page: 23628-23639

3 . 7 4 5

JCR@2019

3 . 4 0 0

JCR@2023

ESI HC Threshold:150

JCR Journal Grade:1

CAS Journal Grade:2

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count: 50

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 0

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