Floorplanning　in　very　large　scale　integrated-circuit　(VLSI)　design　is　the　first　phase　in　the　process　of　designing　the　physical　layout　of　a　chip.　This　makes　the　floorplanning　problem　of　paramount　importance,　since　it　determines　the　performance,　size,　yield,　and　reliability　of　VLSI　chips　[1].　From　the　computational　point　of　view,　the　VLSI　floorplanning　is　an　NP-hard　problem.　In　this　paper,　we　present　a　hybrid　simulated　annealing　algorithm　(HSA)　for　nonslicing　VLSI　floorplanning.　The　HSA　uses　a　new　greedy　method　to　construct　an　initial　B*-tree,　a　new　operation　on　the　B*-tree　to　explore　the　search　space,　and　a　novel　bias　search　strategy　to　balance　global　exploration　and　local　exploitation.　Experimental　results　on　Microelectronic　Center　of　North　Carolina　(MCNC)　benchmarks　[29]　show　that　the　HSA　can　quickly　produce　optimal　or　nearly　optimal　solutions　for　all　the　tested　problems.