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学者姓名：王少昊
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无片外电容低压差线性稳压器(Low-Dropout Regulator,LDO)具有输出纹波小、集成度高等优势.为了克服仅将运算放大器作为误差放大器(Error Amplifier,EA)时LDO瞬态响应较慢的问题,可在运算放大器后级联多级反相器并增加输出反馈电容来改善EA的响应速度.但是当多级反相器仅采用标准阈值电压晶体管时,该EA方案中的静态功耗较高且在瞬态响应期间晶体管容易进线性区.本文提出一种采用混合阈值两级反相器的无片外电容LDO结构,通过在末级反相器中采用高阈值电压晶体管替代相同尺寸的标准阈值晶体管,能够将静态电流降低 75%的同时仅损失约 20%的瞬态响应性能.此外,设计中还加入了阈值电压修调(Threshold Voltage Modulation,TVM)模块,避免高阈值电压晶体管在瞬态响应过程中关断.本文采用SMIC 55nmCMOS工艺对提出的LDO设计进行了仿真.结果表明,该LDO设计在输入、输出电压分别为1.2 V和1.1 V时,整体静态电流仅10 μA,实现了低功耗性能.当负载电流在 30 ns内发生了 20 mA的跳变时,其输出上冲电压为 36 mV,恢复时间为 36 ns.此外,该LDO的线性和负载调整率分别为 0.17 mV/V和 0.2 μV/mA,低频时电源抑制比为-98 dB.
Keyword ：
低压差线性稳压器 低压差线性稳压器 低静态电流 低静态电流 快速瞬态响应 快速瞬态响应 混合阈值反相器 混合阈值反相器
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| GB/T 7714 | 盛祥和 , 郭少威 , 卢杨 et al. 基于混合阈值反相器的低功耗无片外电容LDO [J]. | 微电子学与计算机 , 2025 , 42 (2) : 120-127 . |
| MLA | 盛祥和 et al. "基于混合阈值反相器的低功耗无片外电容LDO" . | 微电子学与计算机 42 . 2 (2025) : 120-127 . |
| APA | 盛祥和 , 郭少威 , 卢杨 , 陈龙 , 杨业成 , 王少昊 . 基于混合阈值反相器的低功耗无片外电容LDO . | 微电子学与计算机 , 2025 , 42 (2) , 120-127 . |
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Recently, memory-augmented neural networks (MANNs) have gained significant attention as a critical solution for few-shot learning (FSL). These networks leverage external memory to store prior knowledge, thereby enhancing classification efficiency. Spin-transfer torque magnetic random access memory (STT-MRAM) is particularly suited for this application due to its compact cell size, excellent data retention, and scalability. In this article, we introduce a STT-MRAM-based near-memory computing (NMC) macro specifically designed for MANNs. Our approach incorporates several key innovations aimed at overcoming challenges in hardware implementation while improving MANN performance as follows: 1) a parallel computing architecture within the NMC to expedite L1 distance computations; 2) a memory invert coding (MIC) and self-termination write (STW) scheme that reduce write operations and energy consumption, addressing the issues of frequent writes and high write currents during the training phase of MANNs; 3) a dynamic offset-compensation sense amplifier (DOC-SA) and high-throughput switch-capacitor (HTSC) readout scheme to improve read accuracy and throughput, tackling low read margins and limited readout bandwidth; 4) an exploration of MANN architectures validates the reusability of the NMC macro. The optimized matching-networks (MCHnets)-based structure achieves an accuracy exceeding 90% in five-way and eight-way Omniglot classification tasks. Fabricated with a 40-nm CMOS technology, our design achieves classification accuracies of 96.37% for eight-way-five-shot tasks and 93.72% for 16-way-five-shot tasks on the Omniglot dataset utilizing the optimized MCHnet, showcasing an impressive energy efficiency of 6.47 TOPS/W at the basis of 16-bit L1 distance computing in the classification tasks of MANN.
Keyword ：
Accuracy Accuracy Computer architecture Computer architecture Few-shot learning (FSL) Few-shot learning (FSL) Magnetic tunneling Magnetic tunneling memory-augmented neural network (MANN) memory-augmented neural network (MANN) near-memory computing (NMC) near-memory computing (NMC) Random access memory Random access memory Resistance Resistance spin-transfer torque magnetic random access memory (STT-MRAM) spin-transfer torque magnetic random access memory (STT-MRAM) Switches Switches Throughput Throughput Torque Torque Training Training Vectors Vectors
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| GB/T 7714 | Zhou, Shengchao , Wang, Yifan , Meng, Hongrui et al. A 40-nm Training-Inference STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration [J]. | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 2025 . |
| MLA | Zhou, Shengchao et al. "A 40-nm Training-Inference STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration" . | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2025) . |
| APA | Zhou, Shengchao , Wang, Yifan , Meng, Hongrui , Wu, Yajun , Ma, Zizhao , Zou, Teng et al. A 40-nm Training-Inference STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration . | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS , 2025 . |
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Lasers emitting visible light based on high harmonic generation (HHG) have significantly enhanced measurement capabilities, enabling new applications across precision metrology, attosecond science, and ultrafast time-resolved spectroscopy. This paper discusses the theoretical framework of HHG with a focus on nonlinear effects, examining in depth second-harmonic generation (SHG) and third-harmonic generation (THG) mechanisms, as well as a thermal nonlinear model for pump stability analysis. The current state of HHG within integrated optical circuits is reviewed, with a particular emphasis on its implementation in high-index doped silica glass micro-ring resonators (HDSG MRRs). We conclude by addressing future directions for optimizing these systems to expand their applicability in advanced photonic technologies, highlighting their potential for innovation in both applied and fundamental sciences.
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| GB/T 7714 | Li, Yuhua , Wang, Shao Hao , Little, Brent E. et al. High Harmonic Generation in Integrated Nonlinear Platforms [J]. | PROGRESS IN ELECTROMAGNETICS RESEARCH-PIER , 2025 , 182 : 27-54 . |
| MLA | Li, Yuhua et al. "High Harmonic Generation in Integrated Nonlinear Platforms" . | PROGRESS IN ELECTROMAGNETICS RESEARCH-PIER 182 (2025) : 27-54 . |
| APA | Li, Yuhua , Wang, Shao Hao , Little, Brent E. , Chu, Sai Tak . High Harmonic Generation in Integrated Nonlinear Platforms . | PROGRESS IN ELECTROMAGNETICS RESEARCH-PIER , 2025 , 182 , 27-54 . |
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This work demonstrates a low thermal budget amorphous InWO (alpha-IWO) thin film transistor (TFT) achieving a subthreshold swing (S.S.) of 40 mV/decade without utilizing a ferroelectric gate oxide. The oxygen vacancies in alpha-IWO induce the formation of an interfacial dipole layer at the surface between alpha-IWO and SiO2/HfO2. The TFT with dipole-rich interface exhibits the S.S. value below 60 mV/decade over 2 decades of drain current. X-ray diffraction (XRD) confirmed the absence of the ferroelectric orthorhombic phase in the HfO2 layer. Besides, the low thermal budget alpha-IWO TFT also exhibits a high field effect mobility of 97 cm(2)/Vs and a large on/off current ratio of 1.8E6, while the process temperature is as low as 300 degrees C.
Keyword ：
alpha-InWO alpha-InWO Annealing Annealing Capacitors Capacitors Hafnium oxide Hafnium oxide high-k engineering high-k engineering Hysteresis Hysteresis interfacial dipole layer interfacial dipole layer Logic gates Logic gates Negative capacitance-like Negative capacitance-like oxygen vacancy oxygen vacancy steep subthreshold swing steep subthreshold swing Stress Stress Thermal stability Thermal stability thin film transistor thin film transistor Thin film transistors Thin film transistors Transistors Transistors X-ray scattering X-ray scattering
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| GB/T 7714 | Zhao, Zefu , Gan, Kai-Jhih , Pan, Shenglin et al. Dipole-Enhanced Low Thermal Budget Amorphous InWO TFT Achieving a Steep Subthreshold Swing of 40 mV/Decade Without Ferroelectric Layer [J]. | IEEE ELECTRON DEVICE LETTERS , 2025 , 46 (3) : 436-439 . |
| MLA | Zhao, Zefu et al. "Dipole-Enhanced Low Thermal Budget Amorphous InWO TFT Achieving a Steep Subthreshold Swing of 40 mV/Decade Without Ferroelectric Layer" . | IEEE ELECTRON DEVICE LETTERS 46 . 3 (2025) : 436-439 . |
| APA | Zhao, Zefu , Gan, Kai-Jhih , Pan, Shenglin , Wang, Shaohao , Li, Tiaoyang , Ruan, Dun-Bao . Dipole-Enhanced Low Thermal Budget Amorphous InWO TFT Achieving a Steep Subthreshold Swing of 40 mV/Decade Without Ferroelectric Layer . | IEEE ELECTRON DEVICE LETTERS , 2025 , 46 (3) , 436-439 . |
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随着新一轮科技革命和产业变革的加速演进,特别是 5G、人工智能、物联网、虚拟现实/增强现实和高性能计算等技术的快速发展,集成电路产业已成为全球技术竞争的焦点.作为集成电路设计领域的顶级国际会议,国际固态电路会议(ISSCC)汇聚了全球最前沿的技术成果.本文对近 5 年ISSCC中国内地和港澳地区论文接收情况进行梳理,并对 2024 年研究成果进行深入分析,涵盖作者背景、研究机构、基金支持、合作情况以及研究趋势等.此外,对这些论文的核心内容进行了翻译和整理,旨在为国内集成电路领域的研究人员提供最新的技术洞察,进而激发创新思维,推动产业进步.
Keyword ：
ISSCC ISSCC 技术洞察 技术洞察 研究趋势 研究趋势 集成电路 集成电路
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| GB/T 7714 | 杨业成 , 王少昊 . ISSCC 2024论文技术热点分析 [J]. | 微纳电子与智能制造 , 2024 , 6 (2) : 1-31 . |
| MLA | 杨业成 et al. "ISSCC 2024论文技术热点分析" . | 微纳电子与智能制造 6 . 2 (2024) : 1-31 . |
| APA | 杨业成 , 王少昊 . ISSCC 2024论文技术热点分析 . | 微纳电子与智能制造 , 2024 , 6 (2) , 1-31 . |
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Chiral noncollinear magnetic nanostructures, such as skyrmions, are intriguing spin configurations with significant potential for magnetic memory technologies. However, the limited availability of 2D magnetic materials that host skyrmions with Curie temperatures above room temperature presents a major challenge for practical implementation. Chromium tellurides exhibit diverse spin configurations and remarkable stability under ambient conditions, making them a promising platform for fundamental spin physics research and the development of innovative 2D spintronic devices. Here, domain structures of Cr0.85Te nanoflakes synthesized via chemical vapor deposition are investigated, using magnetic force microscopy at room temperature. The results reveal that the domain width of the as-grown nanoflakes scales with the square root of their thicknesses. Notably, the emergence and annihilation of skyrmions are observed, which can be reversibly controlled by external magnetic fields and thermal excitation in ambient air. Micromagnetic simulations suggest that the emergence of skyrmions in Cr0.85Te nanoflakes arises from inversion symmetry breaking due to compositional gradients across the sample thickness, rather than the interfacial Dzyaloshinskii-Moriya interaction. These findings provide new insights into the mechanisms underlying skyrmion formation in 2D ferromagnets and open exciting possibilities for manipulating domain structures at room temperature, offering practical pathways for developing next-generation spintronic devices.
Keyword ：
Cr0.85Te nanoflakes Cr0.85Te nanoflakes magnetic domain evolution magnetic domain evolution magnetic force microscopy magnetic force microscopy room temperature 2D ferromagnetic room temperature 2D ferromagnetic skyrmions skyrmions
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| GB/T 7714 | Ni, Yan , Guo, Yongxiang , Jiang, Yuan-Yuan et al. Emergent Skyrmions in Cr0.85Te nanoflakes at Room Temperature [J]. | SMALL , 2024 , 21 (5) . |
| MLA | Ni, Yan et al. "Emergent Skyrmions in Cr0.85Te nanoflakes at Room Temperature" . | SMALL 21 . 5 (2024) . |
| APA | Ni, Yan , Guo, Yongxiang , Jiang, Yuan-Yuan , Huang, Ting , Mu, Qiuxuan , Hou, Feiyan et al. Emergent Skyrmions in Cr0.85Te nanoflakes at Room Temperature . | SMALL , 2024 , 21 (5) . |
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Short-channel-length thin-film amorphous oxide semiconductor field-effect transistor (AOSFET) two-transistor zero-capacitor (2T0C) gain cell (GC) memories are one of the promising technologies for three-dimensional integrated memories. 2T0C with a high-threshold voltage write transistor and a low-threshold voltage read transistor can achieve tens of thousands of seconds of retention time and low power consumption. However, the low threshold voltage of the read transistor leads to an increasing leakage current from the unselected data cells, which reduces the read margin. In this paper, we propose using a pre-charge sense amplifier (PCSA) to reduce leakage current and enhance the read margin. A reference generation circuit is also proposed to enhance the read accuracy. The simulation results show that the proposed PCSA increases the read margin to 168 mV. For the large array with 128 memory cells in a column, a 90 mV read margin can still be achieved compared to the 55 mV in the conventional SA setup.
Keyword ：
amorphous oxide semiconductor amorphous oxide semiconductor Gain-cell DRAM Gain-cell DRAM Sense amplifier Sense amplifier
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| GB/T 7714 | Zhu, Zi Jie , Yang, Ye Cheng , Zheng, Ling Feng et al. ReadMagin Enhanced PCSA for AOSFET 2T0C Gain Cell Memory [J]. | 2024 9TH INTERNATIONAL CONFERENCE ON ELECTRONIC TECHNOLOGY AND INFORMATION SCIENCE, ICETIS 2024 , 2024 : 57-61 . |
| MLA | Zhu, Zi Jie et al. "ReadMagin Enhanced PCSA for AOSFET 2T0C Gain Cell Memory" . | 2024 9TH INTERNATIONAL CONFERENCE ON ELECTRONIC TECHNOLOGY AND INFORMATION SCIENCE, ICETIS 2024 (2024) : 57-61 . |
| APA | Zhu, Zi Jie , Yang, Ye Cheng , Zheng, Ling Feng , Wang, Shao Hao . ReadMagin Enhanced PCSA for AOSFET 2T0C Gain Cell Memory . | 2024 9TH INTERNATIONAL CONFERENCE ON ELECTRONIC TECHNOLOGY AND INFORMATION SCIENCE, ICETIS 2024 , 2024 , 57-61 . |
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Magnetic random-access memory (MRAM)-based computing-in-memory (CIM) schemes can be divided into write-based CIM and read-based CIM. Compared with read-based CIM, the write-based CIM can perform more operations such as AND, OR, majority (MAJ) gate, and full adder (FA). However, write-based CIM schemes require a large number of memory cells and multiple processing cycles. In this paper, we proposed a compact write-based CIM scheme by using a one transistor one high-speed switch magnetic tunnel junction (1T-1HSS-MTJ) memory cell to implement NAND, NOR, XOR, and MAJ gates within two write cycles and one read cycle. Moreover, we also demonstrated that FA operation can also be performed using three 1T-1HSS-MTJ cells within six cycles. According to the simulation results performed using the SMIC 40 nm CMOS process and the HSS-MTJ SPICE model, we have demonstrated that these logic functions can be achieved. When compared to the write-based CIM using SOT-MRAM, the proposed CIM requires fewer cells and shorter latency to achieve the same logic operations.
Keyword ：
computing-in-memory computing-in-memory full adder full adder magnetic RAM magnetic RAM non-volatile memory non-volatile memory
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| GB/T 7714 | Lu, Yang , Wang, Zhi Yuan , Yang, Ye Cheng et al. Compact Write-Based Computing-in-Memory (CIM) using High Speed Switching (HSS) MRAM [J]. | 2024 9TH INTERNATIONAL CONFERENCE ON ELECTRONIC TECHNOLOGY AND INFORMATION SCIENCE, ICETIS 2024 , 2024 : 666-670 . |
| MLA | Lu, Yang et al. "Compact Write-Based Computing-in-Memory (CIM) using High Speed Switching (HSS) MRAM" . | 2024 9TH INTERNATIONAL CONFERENCE ON ELECTRONIC TECHNOLOGY AND INFORMATION SCIENCE, ICETIS 2024 (2024) : 666-670 . |
| APA | Lu, Yang , Wang, Zhi Yuan , Yang, Ye Cheng , Wang, Shao Hao . Compact Write-Based Computing-in-Memory (CIM) using High Speed Switching (HSS) MRAM . | 2024 9TH INTERNATIONAL CONFERENCE ON ELECTRONIC TECHNOLOGY AND INFORMATION SCIENCE, ICETIS 2024 , 2024 , 666-670 . |
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The rising of big data and artificial intelligence applications requires embedded memory with higher density, lower power consumption, and wider bandwidth. Embedded dynamic random-access memory (eDRAM) are one of the promising embedded memory technologies. Recent advances in thin-film amorphous oxide semiconductor field-effect transistors (AOSFET) have enabled two-transistor-zero-capacitor (2T0C) gain cell eDRAMs to have three-dimensional integration capability and ultra-long retention time. However, 2T0C gain cell eDRAMs are still facing read accuracy challenges. In this paper, we explored the statistical distribution characteristics of storage node (SN) charges during the retention and read phases by conducting perturbation analysis on the 2T0C GC eDRAM. Furthermore, we proposed a retention channel model and a read channel model for the 2T0C GC eDRAM. The Monte Carlo circuit simulation results indicate that both the retention channel and read channel can well describe the statistical properties of retention errors and read errors in the 2T0C GC eDRAM. Both channel models can be used to enhance the overall reliability of the GC eDRAM.
Keyword ：
Channel modeling Channel modeling eDRAM eDRAM Gain cell Gain cell
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| GB/T 7714 | Xu, Yu Ting , Zheng, Xiao Bo , Wang, Shao Hao . Channel Modeling for 2T0C Gain-Cell eDRAM [J]. | 2024 9TH INTERNATIONAL CONFERENCE ON ELECTRONIC TECHNOLOGY AND INFORMATION SCIENCE, ICETIS 2024 , 2024 : 45-49 . |
| MLA | Xu, Yu Ting et al. "Channel Modeling for 2T0C Gain-Cell eDRAM" . | 2024 9TH INTERNATIONAL CONFERENCE ON ELECTRONIC TECHNOLOGY AND INFORMATION SCIENCE, ICETIS 2024 (2024) : 45-49 . |
| APA | Xu, Yu Ting , Zheng, Xiao Bo , Wang, Shao Hao . Channel Modeling for 2T0C Gain-Cell eDRAM . | 2024 9TH INTERNATIONAL CONFERENCE ON ELECTRONIC TECHNOLOGY AND INFORMATION SCIENCE, ICETIS 2024 , 2024 , 45-49 . |
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近年来,数据密集型应用对存储器的存储密度和功耗等性能提出了更高的要求.传统的嵌入式缓存采用6T-SRAM和1T1C-eDRAM技术难以提升存储密度,且存在较高的背景功率.其中,6T-SRAM的背景功率主要来自晶体管的高泄漏电流,1T1C-eDRAM则主要来自刷新功耗.非晶氧化物半导体(AOSFET)因其极低的泄漏电流和三维集成潜力备受关注.(AOSFET)2T0C-eDRAM是下一代嵌入式缓存技术的有力竞争者.针对当前缺乏功耗分析方法的现状,本文建立了2T0C-eDRAM的读写功耗、刷新功率和泄漏功率模型,并将其集成到定制化NVSim模块中,实现了对AOSFET 2T0C-eDRAM存储系统的功耗分析.仿真结果表明,在大容量存储阵列中,AOSFET 2T0C-eDRAM的读写功耗会略低于6T-SRAM、1T1C-eDRAM和硅基2T0C-eDRAM,其背景功率(刷新功率和泄漏功率)仅为6T-SRAM的1/6,1T1C-eDRAM的1/10,硅基2T0C-eDRAM的1/10.
Keyword ：
2T0C GC-eDRAM 2T0C GC-eDRAM AOSFET AOSFET 仿真方法 仿真方法 功耗 功耗 存储系统 存储系统
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| GB/T 7714 | 李伟 , 陈龙 , 杨业成 et al. 面向AOSFET增益单元的存储系统功耗分析研究 [J]. | 电子制作 , 2024 , 32 (14) : 36-39,10 . |
| MLA | 李伟 et al. "面向AOSFET增益单元的存储系统功耗分析研究" . | 电子制作 32 . 14 (2024) : 36-39,10 . |
| APA | 李伟 , 陈龙 , 杨业成 , 郑凌丰 , 王少昊 . 面向AOSFET增益单元的存储系统功耗分析研究 . | 电子制作 , 2024 , 32 (14) , 36-39,10 . |
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