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学者姓名：魏聪
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Abstract ：
This paper describes the analysis and design of a discrete-time (DT) fully dynamic 3-0 multi-stage noise-shaping (MASH) delta-sigma (Delta Sigma) analog-to-digital converter (ADC). Through system-level analysis, error source analysis, nonlinearity analysis and modeling of the integrators, and detailed considerations for circuit implementation, the trade-offs between design parameters in the 3-0 MASH Delta Sigma ADC were evaluated. The proposed ADC is fabricated and measured in a 180 nm CMOS process, achieving a DR, peak SNDR, and SFDR of 100.2 dB, 98.5 dB, and 116.7 dB, respectively, within a 2.56 kHz bandwidth, consuming only 20.1 mu W. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR are 179.6 dB and 181.3 dB, respectively. The measurement results of the prototype 3-0 MASH Delta Sigma ADC closely matched the theoretical predictions. This consistency between the measurements and the theoretical analysis confirms the reliability of the design approach in achieving the expected performance.
Keyword ：
Active filters Active filters analog-to-digital converter (ADC) analog-to-digital converter (ADC) Circuits Circuits delta-sigma (Delta Sigma) delta-sigma (Delta Sigma) Digital filters Digital filters discrete-time (DT) discrete-time (DT) Energy efficiency Energy efficiency Gain Gain Multi-stage noise shaping Multi-stage noise shaping Multi-stage noise-shaping (MASH) Multi-stage noise-shaping (MASH) Noise Noise Power demand Power demand Quantization (signal) Quantization (signal) Transfer functions Transfer functions
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| GB/T 7714 | Wei, Cong , Huang, Lijie , Wei, Rongshan et al. Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range [J]. | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2025 . |
| MLA | Wei, Cong et al. "Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range" . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2025) . |
| APA | Wei, Cong , Huang, Lijie , Wei, Rongshan , Lu, Xiaoqiang , Tan, Zhichao . Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2025 . |
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Abstract ：
针对物联网传感器难以同时满足高分辨率与低功耗的瓶颈问题,本文设计了一种伪三阶离散时间del-ta-sigma调制器.该架构将一阶无源噪声整形SAR(Successive Approximation Register)量化器嵌入传统二阶delta-sigma调制器以实现更强的噪声整形能力.本文设计允许系统在更低的过采样率(Over Sampling Ratio,OSR)下获取更高的峰值SQNR(Signal-to-Quantizing Noise Ratio),有效缓解了系统精度和功耗之间的设计矛盾,并且减少了有源积分器的使用.针对传统有源加法器高功耗和无源加法器存在衰减不确定性的问题,本文提出了一种新型前馈求和量化电路,它具有对衰减不敏感的优势并且降低了第二级有源积分器的驱动压力,这进一步降低了系统的功耗.本文提出的del-ta-sigma调制器采用180 nm CMOS(Complementary Metal Oxide Semiconductor)工艺制造并测试.在电源电压1.4 V下,芯片测试功耗为47.2μW.在带宽为8 kHz的测试条件下,调制器的DR(Dynamic Range)、峰值SNDR(Signal-to-Noise and Distortion Ratio)和SFDR(Spurious-Free Dynamic Range)分别为97.2dB,96.6dB和114.4dB.因此,Schreier和Walden的SNDR FoM(Figure of Merit)优值达到了178.9dB和0.053 pJ/step.本文提出的伪三阶delta-sigma调制器在功耗和分辨率之间实现了较好的权衡,为物联网领域的低功耗高分辨率调制器设计提供了较好的解决方案.
Keyword ：
delta-sigma调制器 delta-sigma调制器 低功耗 低功耗 物联网 物联网 高分辨率 高分辨率
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| GB/T 7714 | 魏聪 , 黄黎杰 , 胡炜 et al. 一种应用于物联网传感器的伪三阶Delta-Sigma调制器 [J]. | 电子学报 , 2024 , 52 (6) : 2123-2130 . |
| MLA | 魏聪 et al. "一种应用于物联网传感器的伪三阶Delta-Sigma调制器" . | 电子学报 52 . 6 (2024) : 2123-2130 . |
| APA | 魏聪 , 黄黎杰 , 胡炜 , 魏榕山 . 一种应用于物联网传感器的伪三阶Delta-Sigma调制器 . | 电子学报 , 2024 , 52 (6) , 2123-2130 . |
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